revd

Reverse Doublewords

REVD <Zd>.Q, <Pg>/M, <Zn>.Q

Reverses 64-bit doublewords within 128-bit quadwords (SVE2).

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

00000101

31:24

101110100

21:13

12:10

9:5

4:0

Format SVE2

Opcode 0x052E8000

Extension SVE2

Operands

Zd
Dest
Pg
Mask
Zn
Src

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x052E8000	REVD <Zd>.Q, <Pg>/M, <Zn>.Q		A64		00000101 \| 0 \| 0 \| 101110100 \| Pg \| Zn \| Zd

Description

Reverse the order of 64-bit doublewords within each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = Reverse(element, swsize);

Z[d, VL] = result;