sclamp

Signed Integer Clamp

SCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

Clamps signed integer elements between min and max (SVE2.1).

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01000100

31:24

size

23:22

20:16

11000

15:11

9:5

4:0

Format SVE2.1

Opcode 0x4400C000

Extension SVE2p1

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xC120C400	SCLAMP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>	A64	11000001 \| size \| 1 \| Zm \| 110001 \| Zn \| Zd \| 0
0xC120CC00	SCLAMP { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T>	A64	11000001 \| size \| 1 \| Zm \| 110011 \| Zn \| Zd \| 0 \| 0
0x4400C000	SCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T>	A64	01000100 \| size \| 0 \| Zm \| 11000 \| 0 \| Zn \| Zd

Description

Clamp each signed element in the destination vector to between the signed minimum value in the corresponding element of the first source vector and the signed maximum value in the corresponding element of the second source vector and destructively write the results in the corresponding elements of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[d, VL];
bits(VL) result;

for e = 0 to elements-1
    integer element1 = SInt(Elem[operand1, e, esize]);
    integer element2 = SInt(Elem[operand2, e, esize]);
    integer element3 = SInt(Elem[operand3, e, esize]);
    integer res = Min(Max(element1, element3), element2);
    Elem[result, e, esize] = res<esize-1:0>;

Z[d, VL] = result;