smullt
SMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
Signed Multiply Long (Top)
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
01000101
31:24
size
23:22
0
21
Zm
20:16
011
15:13
1
12
0
11
1
10
Zn
9:5
Zd
4:0
Related
More in SVE2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x45007400 | SMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | A64 | 01000101 | size | 0 | Zm | 011 | 1 | 0 | 1 | Zn | Zd | ||
| 0x44A0C400 | SMULLT <Zd>.S, <Zn>.H, <Zm>.H[<imm>] | A64 | 01000100 | 1 | 0 | 1 | i3h | Zm | 110 | 0 | i3l | 1 | Zn | Zd | ||
| 0x44E0C400 | SMULLT <Zd>.D, <Zn>.S, <Zm>.S[<imm>] | A64 | 01000100 | 1 | 1 | 1 | i2h | Zm | 110 | 0 | i2l | 1 | Zn | Zd |
Description
Multiply the corresponding odd-numbered signed elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;
for e = 0 to elements-1
integer element1 = SInt(Elem[operand1, 2*e + 1, esize DIV 2]);
integer element2 = SInt(Elem[operand2, 2*e + 1, esize DIV 2]);
integer res = element1 * element2;
Elem[result, e, esize] = res<esize-1:0>;
Z[d, VL] = result;