srhadd

SRHADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Signed Rounding Halving Add.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01000100

31:24

size

23:22

010

21:19

100

15:13

12:10

9:5

Zdn

4:0

Format SVE2

Opcode 0x44148000

Extension SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0E201400	SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 \| Q \| 0 \| 01110 \| size \| 1 \| Rm \| 00010 \| 1 \| Rn \| Rd
0x44148000	SRHADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>		A64		01000100 \| size \| 010 \| 1 \| 0 \| 0 \| 100 \| Pg \| Zm \| Zdn

Description

Add active signed elements of the first source vector to corresponding signed elements of the second source vector, shift right one bit, and destructively place the rounded results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    integer element1 = SInt(Elem[operand1, e, esize]);
    integer element2 = SInt(Elem[operand2, e, esize]);
    if ActivePredicateElement(mask, e, esize) then
        integer res = (element1 + element2 + 1) >> 1;
        Elem[result, e, esize] = res<esize-1:0>;
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;