sqneg

SQNEG <Zd>.<T>, <Pg>/M, <Zn>.<T>

Signed Saturating Negate.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01000100
31:24
size
23:22
00
21:20
1
19
0
18
0
17
1
16
101
15:13
Pg
12:10
Zn
9:5
Zd
4:0
 
Format SVE2
Opcode 0x4409A000
Extension SVE2

Related

More in SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7E207800 SQNEG <V><d>, <V><n> A64 01 | 1 | 11110 | size | 10000 | 00111 | 10 | Rn | Rd
0x2E207800 SQNEG <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | size | 10000 | 00111 | 10 | Rn | Rd
0x4409A000 SQNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 01000100 | size | 00 | 1 | 0 | 0 | 1 | 101 | Pg | Zn | Zd

Description

Negate the signed integer value in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer element = SInt(Elem[operand, e, esize]);
        element = -element;
        Elem[result, e, esize] = SignedSat(element, esize);

Z[d, VL] = result;