srshl
SRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
Signed Rounding Shift Left.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
01000100
31:24
size
23:22
00
21:20
0
19
0
18
1
17
0
16
100
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
Related
More in SVE2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5EE05400 | SRSHL D<d>, D<n>, D<m> | A64 | 01 | 0 | 11110 | 11 | 1 | Rm | 010 | 1 | 0 | 1 | Rn | Rd | ||
| 0x0E205400 | SRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 010 | 1 | 0 | 1 | Rn | Rd | ||
| 0xC120A220 | SRSHL { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101000 | 10 | 00 | 1 | Zdn | 0 | ||
| 0xC120AA20 | SRSHL { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101010 | 10 | 00 | 1 | Zdn | 0 | 0 | ||
| 0xC120B220 | SRSHL { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } | A64 | 11000001 | size | 1 | Zm | 0101100 | 10 | 00 | 1 | Zdn | 0 | ||
| 0xC120BA20 | SRSHL { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } | A64 | 11000001 | size | 1 | Zm | 00101110 | 10 | 00 | 1 | Zdn | 0 | 0 | ||
| 0x44028000 | SRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 01000100 | size | 00 | 0 | 0 | 1 | 0 | 100 | Pg | Zm | Zdn |
Description
Shift active signed elements of the first source vector by corresponding elements of the second source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Inactive elements in the destination vector register remain unmodified.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
integer element = SInt(Elem[operand1, e, esize]);
integer shift = ShiftSat(SInt(Elem[operand2, e, esize]), esize);
integer res;
if shift >= 0 then
res = element << shift;
else
shift = -shift;
res = (element + (1 << (shift - 1))) >> shift;
Elem[result, e, esize] = res<esize-1:0>;
else
Elem[result, e, esize] = Elem[operand1, e, esize];
Z[dn, VL] = result;