sqadd
SQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
Signed Saturating Add.
Pseudocode Operation
No pseudocode available.
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5E200C00 | SQADD <V><d>, <V><n>, <V><m> | A64 | 01 | 0 | 11110 | size | 1 | Rm | 00001 | 1 | Rn | Rd | ||
| 0x0E200C00 | SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 00001 | 1 | Rn | Rd | ||
| 0x44188000 | SQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 01000100 | size | 011 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn | ||
| 0x2524C000 | SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} | A64 | 00100101 | size | 100 | 10 | 0 | 11 | sh | imm8 | Zdn | ||
| 0x04201000 | SQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 1 | Zm | 000 | 10 | 0 | Zn | Zd |
Description
Signed saturating add all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. This instruction is unpredicated.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;
for e = 0 to elements-1
integer element1 = Int(Elem[operand1, e, esize], unsigned);
integer element2 = Int(Elem[operand2, e, esize], unsigned);
(Elem[result, e, esize], -) = SatQ(element1 + element2, esize, unsigned);
Z[d, VL] = result;