sqshrnb
SQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
Signed Saturating Shift Right Narrow (Bottom)
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
010001010
31:23
tszh
22
1
21
tszl
20:19
imm3
18:16
00
15:14
1
13
0
12
0
11
0
10
Zn
9:5
Zd
4:0
Related
More in SVE2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x45202000 | SQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const> | A64 | 010001010 | tszh | 1 | tszl | imm3 | 00 | 1 | 0 | 0 | 0 | Zn | Zd |
Description
Shift each signed integer value in the source vector elements right by an immediate value, and place the truncated results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV (2 * esize);
bits(VL) operand = Z[n, VL];
bits(VL) result;
for e = 0 to elements-1
bits(2*esize) element = Elem[operand, e, 2*esize];
integer res = SInt(element) >> shift;
Elem[result, 2*e + 0, esize] = SignedSat(res, esize);
Elem[result, 2*e + 1, esize] = Zeros(esize);
Z[d, VL] = result;