smulh

SMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Signed Multiply High.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
00000100
31:24
size
23:22
0100
21:18
1
17
0
16
000
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
 
Format SVE2
Opcode 0x04120000
Extension SVE2

Related

Other forms of smulh

  • smulh Signed Multiply High, Base

Across architectures

Multiply High : how x86, ARM, RISC-V, and PowerISA each do this.

More in SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x9B407C00 SMULH <Xd>, <Xn>, <Xm> A64 1 | 00 | 11011 | 0 | 10 | Rm | 0 | 11111 | Rn | Rd
0x04120000 SMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 0100 | 1 | 0 | 000 | Pg | Zm | Zdn
0x04206800 SMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000100 | size | 1 | Zm | 0110 | 1 | 0 | Zn | Zd

Description

Widening multiply signed integer values in active elements of the first source vector by corresponding elements of the second source vector and destructively place the high half of the result in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    integer element1 = Int(Elem[operand1, e, esize], unsigned);
    integer element2 = Int(Elem[operand2, e, esize], unsigned);
    if ActivePredicateElement(mask, e, esize) then
        integer product = (element1 * element2) >> esize;
        Elem[result, e, esize] = product<esize-1:0>;
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;