sqdmlalt

SQDMLALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

Signed Saturating Doubling Multiply-Add Long (Top)

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01000100

31:24

size

23:22

20:16

0110

15:12

9:5

Zda

4:0

Format SVE2

Opcode 0x44006400

Extension SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x44006400	SQDMLALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>	A64	01000100 \| size \| 0 \| Zm \| 0110 \| 0 \| 1 \| Zn \| Zda
0x44A02400	SQDMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]	A64	01000100 \| 1 \| 0 \| 1 \| i3h \| Zm \| 001 \| 0 \| i3l \| 1 \| Zn \| Zda
0x44E02400	SQDMLALT <Zda>.D, <Zn>.S, <Zm>.S[<imm>]	A64	01000100 \| 1 \| 1 \| 1 \| i2h \| Zm \| 001 \| 0 \| i2l \| 1 \| Zn \| Zda

Description

Multiply then double the corresponding odd-numbered signed elements of the first and second source vectors. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1) to (2(N-1) )-1. Then destructively add to the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result = Z[da, VL];

for e = 0 to elements-1
    integer element1 = SInt(Elem[operand1, 2 * e + sel1, esize DIV 2]);
    integer element2 = SInt(Elem[operand2, 2 * e + sel2, esize DIV 2]);
    integer element3 = SInt(Elem[result, e, esize]);
    integer product = SInt(SignedSat(2 * element1 * element2, esize));
    Elem[result, e, esize] = SignedSat(element3 + product, esize);

Z[da, VL] = result;