st1d

Scatter Store Doublewords (SVE)

ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]

Stores doublewords to non-contiguous memory addresses.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
1110010
31:25
1
24
1
23
01
22:21
Zm
20:16
101
15:13
Pg
12:10
Rn
9:5
Zt
4:0
 
Format SVE Scatter
Opcode 0xE5A0A000
Extension SVE

Operands

  • Zt
    Src
  • Xn
    Base
  • Zm
    Offsets

Related

Other forms of st1d

  • st1d SVE Store Contiguous Doublewords

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xA0606000 ST1D { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000110 | imm4 | 0 | 1 | 1 | PNg | Rn | Zt | 0
0xA060E000 ST1D { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000110 | imm4 | 1 | 1 | 1 | PNg | Rn | Zt | 0 | 0
0xA0206000 ST1D { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] A64 10100000001 | Rm | 0 | 1 | 1 | PNg | Rn | Zt | 0
0xA020E000 ST1D { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] A64 10100000001 | Rm | 1 | 1 | 1 | PNg | Rn | Zt | 0 | 0
0xA1606000 ST1D { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010110 | imm4 | 0 | 1 | 1 | PNg | Rn | T | 0 | Zt
0xA160E000 ST1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010110 | imm4 | 1 | 1 | 1 | PNg | Rn | T | 0 | 0 | Zt
0xA1206000 ST1D { <Zt1>.D, <Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] A64 10100001001 | Rm | 0 | 1 | 1 | PNg | Rn | T | 0 | Zt
0xA120E000 ST1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] A64 10100001001 | Rm | 1 | 1 | 1 | PNg | Rn | T | 0 | 0 | Zt
0xE5C0A000 ST1D { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}] A64 1110010 | 1 | 1 | 10 | imm5 | 101 | Pg | Zn | Zt
0xE5E0E000 ST1D { <Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 1110010 | 1 | 1 | 11 | 0 | imm4 | 111 | Pg | Rn | Zt
0xE5C0E000 ST1D { <Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 1110010 | 1 | 1 | 10 | 0 | imm4 | 111 | Pg | Rn | Zt
0xE5E04000 ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] A64 1110010 | 11 | 1 | 1 | Rm | 010 | Pg | Rn | Zt
0xE5C04000 ST1D { <Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #3] A64 1110010 | 11 | 1 | 0 | Rm | 010 | Pg | Rn | Zt
0xE5A08000 ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3] A64 1110010 | 1 | 1 | 01 | Zm | 1 | xs | 0 | Pg | Rn | Zt

Description

Scatter store of doublewords from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 8. Inactive elements are not written to memory. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) offset;
bits(VL) src;
constant integer mbytes = msize DIV 8;
boolean contiguous = FALSE;
boolean nontemporal = FALSE;
boolean tagchecked = TRUE;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];
    offset = Z[m, VL];
    src = Z[t, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned);
        bits(64) addr = GenerateAddress(base, off << scale, accdesc);
        Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;