uaddlt

UADDLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

Unsigned Add Long (Top)

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01000101
31:24
size
23:22
0
21
Zm
20:16
00
15:14
0
13
0
12
1
11
1
10
Zn
9:5
Zd
4:0
 
Format SVE2
Opcode 0x45000C00
Extension SVE2

Related

More in SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x45000C00 UADDLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> A64 01000101 | size | 0 | Zm | 00 | 0 | 0 | 1 | 1 | Zn | Zd

Description

Add the corresponding odd-numbered unsigned elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;

for e = 0 to elements-1
    integer element1 = Int(Elem[operand1, 2*e + sel1, esize DIV 2], unsigned);
    integer element2 = Int(Elem[operand2, 2*e + sel2, esize DIV 2], unsigned);
    integer res = element1 + element2;
    Elem[result, e, esize] = res<esize-1:0>;

Z[d, VL] = result;