uqrshl

Unsigned Saturating Rounding Shift Left (SVE2)

UQRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Unsigned saturating, rounding left shift.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01000100
31:24
size
23:22
00
21:20
1
19
0
18
1
17
1
16
100
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
 
Format SVE2 Shift
Opcode 0x440B8000
Extension SVE2

Operands

  • Zdn
    Dest/Src
  • Zm
    Shift

Related

More in SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7E205C00 UQRSHL <V><d>, <V><n>, <V><m> A64 01 | 1 | 11110 | size | 1 | Rm | 010 | 1 | 1 | 1 | Rn | Rd
0x2E205C00 UQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 010 | 1 | 1 | 1 | Rn | Rd
0x440B8000 UQRSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01000100 | size | 00 | 1 | 0 | 1 | 1 | 100 | Pg | Zm | Zdn

Description

Shift active unsigned elements of the first source vector by corresponding elements of the second source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer element = UInt(Elem[operand1, e, esize]);
        integer shift = ShiftSat(SInt(Elem[operand2, e, esize]), esize);
        integer res;
        if shift >= 0 then
            res = element << shift;
        else
            shift = -shift;
            res = (element + (1 << (shift - 1))) >> shift;
        Elem[result, e, esize] = UnsignedSat(res, esize);
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;