whilewr
While Write/Read (SVE2)
WHILEWR <Pd>.<T>, <Xn>, <Xm>
Generates a predicate for concurrent write/read loop iterations.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
00100101
31:24
size
23:22
1
21
Rm
20:16
001100
15:10
Rn
9:5
0
4
Pd
3:0
Operands
-
Pd
Predicate -
Xn
Start -
Xm
End
Related
More in SVE2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x25203000 | WHILEWR <Pd>.<T>, <Xn>, <Xm> | A64 | 00100101 | size | 1 | Rm | 001100 | Rn | 0 | Pd |
Description
This instruction checks two addresses for a conflict or overlap between address ranges of the form [addr,addr+VL÷8), where VL is the accessible vector length in bits, that could result in a loop-carried dependency through memory due to the use of these addresses by contiguous load and store instructions within the same iteration of a loop. Generate a predicate whose elements are true while the addresses cannot conflict within the same iteration, and false thereafter. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = Ones(PL);
bits(64) src1 = X[n, 64];
bits(64) src2 = X[m, 64];
integer operand1 = UInt(src1);
integer operand2 = UInt(src2);
bits(PL) result;
constant integer psize = esize DIV 8;
integer diff = (operand2 - operand1) DIV (esize DIV 8);
for e = 0 to elements-1
if diff <= 0 || e < diff then
Elem[result, e, psize] = ZeroExtend('1', psize);
else
Elem[result, e, psize] = ZeroExtend('0', psize);
PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;