sdivr
SDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
Signed Integer Divide Reverse.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
00000100
31:24
size
23:22
0101
21:18
1
17
0
16
000
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
Related
More in SVE
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x04160000 | SDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 0101 | 1 | 0 | 000 | Pg | Zm | Zdn |
Description
Signed reversed divide active elements of the second source vector by corresponding elements of the first source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;
for e = 0 to elements-1
integer element1 = Int(Elem[operand1, e, esize], unsigned);
if ActivePredicateElement(mask, e, esize) then
integer element2 = Int(Elem[operand2, e, esize], unsigned);
integer quotient;
if element1 == 0 then
quotient = 0;
else
quotient = RoundTowardsZero(Real(element2) / Real(element1));
Elem[result, e, esize] = quotient<esize-1:0>;
else
Elem[result, e, esize] = Elem[operand1, e, esize];
Z[dn, VL] = result;