rdffr

RDFFR <Pd>.B

Read First-Fault Register.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

00100101

31:24

011001111100

21:10

000000

9:4

3:0

Format SVE

Opcode 0x2519F000

Extension SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2519F000	RDFFR <Pd>.B		A64		00100101 \| 0 \| 0 \| 011001111100 \| 000000 \| Pd
0x2518F000	RDFFR <Pd>.B, <Pg>/Z		A64		00100101 \| 0 \| 0 \| 011000111100 \| 0 \| Pg \| 0 \| Pd

Description

Read the first-fault register (FFR) and place in the destination predicate without predication. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
bits(PL) ffr = FFR[PL];
P[d, PL] = ffr;