prfd
PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
Prefetch Gather (Double)
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
11000100011
31:21
Zm
20:16
1
15
1
14
1
13
Pg
12:10
Rn
9:5
0
4
prfop
3:0
Related
More in SVE
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x8580E000 | PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}] | A64 | 1000010 | 1 | 1 | 00 | imm5 | 111 | Pg | Zn | 0 | prfop | ||
| 0xC580E000 | PRFD <prfop>, <Pg>, [<Zn>.D{, #<imm>}] | A64 | 1100010 | 1 | 1 | 00 | imm5 | 111 | Pg | Zn | 0 | prfop | ||
| 0x85C06000 | PRFD <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] | A64 | 1000010111 | imm6 | 0 | 1 | 1 | Pg | Rn | 0 | prfop | ||
| 0x8580C000 | PRFD <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3] | A64 | 1000010 | 1 | 1 | 00 | Rm | 110 | Pg | Rn | 0 | prfop | ||
| 0x84206000 | PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #3] | A64 | 100001000 | xs | 1 | Zm | 0 | 1 | 1 | Pg | Rn | 0 | prfop | ||
| 0xC4206000 | PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3] | A64 | 110001000 | xs | 1 | Zm | 0 | 1 | 1 | Pg | Rn | 0 | prfop | ||
| 0xC460E000 | PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3] | A64 | 11000100011 | Zm | 1 | 1 | 1 | Pg | Rn | 0 | prfop |
Description
Gather prefetch of doublewords from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then multiplied by 8. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
Operation
CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(64) base;
bits(VL) offset;
if AnyActiveElement(mask, esize) then
base = if n == 31 then SP[] else X[n, 64];
offset = Z[m, VL];
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned);
bits(64) addr = base + (off << scale);
Hint_Prefetch(addr, pref_hint, level, stream);