orn

ORN <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B

Predicate OR NOT

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

00100101

31:24

21:20

19:16

15:14

13:10

8:5

3:0

Format SVE

Opcode 0x25804010

Extension SVE

Other forms of orn

orn Bitwise OR NOT
orn Vector Bitwise OR NOT

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x0EE01C00	ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>	A64	0 \| Q \| 0 \| 01110 \| 11 \| 1 \| Rm \| 00011 \| 1 \| Rn \| Rd
0x2A200000	ORN <Wd>, <Wn>, <Wm>{, <shift> #<amount>}	A64	0 \| 01 \| 01010 \| shift \| 1 \| Rm \| imm6 \| Rn \| Rd
0xAA200000	ORN <Xd>, <Xn>, <Xm>{, <shift> #<amount>}	A64	1 \| 01 \| 01010 \| shift \| 1 \| Rm \| imm6 \| Rn \| Rd
0x05000000	ORN <Zdn>.<T>, <Zdn>.<T>, #<const>	A64	00000101 \| 0 \| 0 \| 0000 \| imm13 \| Zdn
0x25804010	ORN <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B	A64	00100101 \| 1 \| 0 \| 00 \| Pm \| 01 \| Pg \| 0 \| Pn \| 1 \| Pd

Description

Bitwise inclusive OR inverted active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(PL) operand1 = P[n, PL];
bits(PL) operand2 = P[m, PL];
bits(PL) result;
constant integer psize = esize DIV 8;

for e = 0 to elements-1
    bit element1 = PredicateElement(operand1, e, esize);
    bit element2 = PredicateElement(operand2, e, esize);
    if ActivePredicateElement(mask, e, esize) then
        Elem[result, e, psize] = ZeroExtend(element1 OR (NOT element2), psize);
    else
        Elem[result, e, psize] = ZeroExtend('0', psize);

if setflags then
    PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;

orn