raddhnb

RADDHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

Rounding Add Narrow High (Bottom)

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01000101

31:24

size

23:22

20:16

011

15:13

9:5

4:0

Format SVE2

Opcode 0x45206800

Extension SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x45206800	RADDHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>		A64		01000101 \| size \| 1 \| Zm \| 011 \| 0 \| 1 \| 0 \| Zn \| Zd

Description

Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant rounded half of the result in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;
constant integer halfesize = esize DIV 2;

for e = 0 to elements-1
    integer element1 = UInt(Elem[operand1, e, esize]);
    integer element2 = UInt(Elem[operand2, e, esize]);
    integer res = ((element1 + element2) + (1 << (halfesize - 1))) >> halfesize;
    Elem[result, 2*e + 0, halfesize] = res<halfesize-1:0>;
    Elem[result, 2*e + 1, halfesize] = Zeros(halfesize);

Z[d, VL] = result;