nand

NAND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B

Predicate NAND

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
00100101
31:24
1
23
0
22
00
21:20
Pm
19:16
01
15:14
Pg
13:10
1
9
Pn
8:5
1
4
Pd
3:0
 
Format SVE
Opcode 0x25804210
Extension SVE

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x25804210 NAND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 1 | 0 | 00 | Pm | 01 | Pg | 1 | Pn | 1 | Pd

Description

Bitwise NAND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(PL) operand1 = P[n, PL];
bits(PL) operand2 = P[m, PL];
bits(PL) result;
constant integer psize = esize DIV 8;

for e = 0 to elements-1
    bit element1 = PredicateElement(operand1, e, esize);
    bit element2 = PredicateElement(operand2, e, esize);
    if ActivePredicateElement(mask, e, esize) then
        Elem[result, e, psize] = ZeroExtend(NOT(element1 AND element2), psize);
    else
        Elem[result, e, psize] = ZeroExtend('0', psize);

if setflags then
    PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;