Base Instructions

159 ARM instructions in this extension - showing 59 per page, page 2 of 2 - click any row for encoding, pseudocode, and full documentation.

Mnemonic ⇅ Syntax Format ⇅ Summary
movz MOVZ <Wd>, #<imm16> {, lsl #<shift>} Data Processing Moves 16-bit immediate to register, zeroing other bits.
msub MSUB <Wd>, <Wn>, <Wm>, <Wa> Data Processing Calculates (Ra - (Rn * Rm)).
nop NOP System Alias Does nothing. Used for padding or timing.
orn ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) ORs register with NOT of shifted register.
orr ORR <Wd|Wsp>, <Wn>, #<imm> Logical (Immediate) ORs register with logical immediate.
orr ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) ORs two registers.
prfm PRFM <prfop>, [<Xn|SP>, #<pimm>] Load/Store Imm Signals the memory system to prefetch data into cache.
prfm PRFM <prfop>, <label> Load Literal Prefetches data from a PC-relative address.
prfm PRFM <prfop>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Prefetches data using a register offset.
rbit RBIT <Wd>, <Wn> Data Processing Reverses the bit order in a register.
rbit RBIT <Xd>, <Xn> Data Processing Reverses the bit order in a 64-bit register.
ret RET {<Xn>} Branch Branches to address in LR (or specified register).
rev REV <Xd>, <Xn> Data Processing Reverses byte order in a 64-bit register.
rev REV <Wd>, <Wn> Data Processing Reverses the byte order in a 32-bit register (Endianness swap).
rev16 REV16 <Wd>, <Wn> Data Processing Reverses bytes in each 16-bit halfword.
rev32 REV32 <Xd>, <Xn> Data Processing Reverses bytes in each 32-bit word (64-bit op).
rorv RORV <Wd>, <Wn>, <Wm> Data Processing Rotates register right by variable amount.
sbc SBC <Wd>, <Wn>, <Wm> Data Processing Subtracts with borrow (Carry - 1).
sbcs SBCS <Wd>, <Wn>, <Wm> Data Processing Subtracts with borrow and updates flags.
sbfm SBFM <Wd>, <Wn>, #<immr>, #<imms> Bitfield Extracts/Inserts bitfield with sign extension.
sdiv SDIV <Wd>, <Wn>, <Wm> Data Processing Divides two signed registers.
sev SEV System Alias Sends an event to all processors in the cluster (wakes up WFE).
sevl SEVL System Alias Sends an event locally to the executing processor.
smaddl SMADDL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Multiplies two 32-bit registers, adds to 64-bit register (64-bit result).
smsubl SMSUBL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Calculates (Xa - (Wn * Wm)) (64-bit result).
smulh SMULH <Xd>, <Xn>, <Xm> Data Processing Multiplies two 64-bit registers, keeps high 64 bits.
stnp STNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Stores two registers, hinting non-temporal data.
stp STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Stores two 32-bit registers.
stp STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] Load/Store Pair Stores two 64-bit registers.
str STR <Wt>, [<Xn|SP>, #<pimm>] Load/Store Imm Stores a register to memory (Immediate offset).
str STR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Stores a register to memory (Register offset).
strb STRB <Wt>, [<Xn|SP>, #<pimm>] Load/Store Stores the low byte of a register.
strb STRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Stores the low byte of a register using register offset.
strh STRH <Wt>, [<Xn|SP>, #<pimm>] Load/Store Stores the low halfword of a register.
strh STRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Stores the low halfword of a register using register offset.
sttr STTR <Wt>, [<Xn|SP>, #<simm>] Load/Store Stores a register as if in EL0 (User mode).
sttrb STTRB <Wt>, [<Xn|SP>, #<simm>] Load/Store Stores a byte as if in EL0.
sttrh STTRH <Wt>, [<Xn|SP>, #<simm>] Load/Store Stores a halfword as if in EL0.
stur STUR <Wt>, [<Xn|SP>, #<simm>] Load/Store Stores a register using an unscaled immediate offset.
sturb STURB <Wt>, [<Xn|SP>, #<simm>] Load/Store Stores a byte using an unscaled immediate offset.
sturh STURH <Wt>, [<Xn|SP>, #<simm>] Load/Store Stores a halfword using an unscaled immediate offset.
sub SUB <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} Data Processing Subtracts extended register from register.
sub SUB <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} Data Processing Subtracts immediate from register.
sub SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Data Processing Subtracts shifted register from register.
subs SUBS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} Data Processing Subtracts extended register and updates flags.
subs SUBS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} Data Processing Subtracts immediate and updates flags.
subs SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Data Processing Subtracts shifted register and updates flags.
sxtb SXTB <Wd>, <Wn> Bitfield Extracts the lowest 8 bits and sign-extends to 32 bits (Alias for SBFM).
sxtw SXTW <Xd>, <Wn> Bitfield Sign-extends a 32-bit register to 64 bits (Alias for SBFM).
tbnz TBNZ <Wt|Xt>, #<imm>, <label> Branch Branches if specified bit is 1.
tbz TBZ <Wt|Xt>, #<imm>, <label> Branch Branches if specified bit is 0.
ubfm UBFM <Wd>, <Wn>, #<immr>, #<imms> Bitfield Extracts/Inserts bitfield (Zero Extend).
udiv UDIV <Wd>, <Wn>, <Wm> Data Processing Divides two unsigned registers.
umaddl UMADDL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Multiplies two 32-bit regs, adds to 64-bit reg (Unsigned).
umsubl UMSUBL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Calculates (Xa - (Wn * Wm)) (Unsigned 64-bit).
umulh UMULH <Xd>, <Xn>, <Xm> Data Processing Multiplies two 64-bit registers, keeps high 64 bits (Unsigned).
wfe WFE System Alias Puts the processor into a low-power state until an event occurs.
wfi WFI System Alias Puts the processor into a low-power state until an interrupt occurs.
yield YIELD System Alias Hints that the current thread is performing a spin-wait loop.