fmul.

Floating Multiply (Record)

fmul. FRT,FRA,FRC

Multiplies the contents of two floating-point registers and places the result into another register.

Encoding

Binary Layout

63

0:5

FRT

6:10

FRA

11:15

00000

16:20

FRC

21:25

25

26:30

Rc

31

 

Format A-form

Opcode 0xFC000032

Extension Floating-Point

Operands

• FRT
  Target FPR
• FRA
  Source FPR A
• FRC
  Source FPR C

Example

fmul f1, f2, f3

// f1 = f2 * f3

Registers Altered

FPSCR, CR1, CR0

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The floating-point operand in register FRA is multiplied by the floating-point operand in register FRC. The result is rounded to the target precision under control of RN and placed into register FRT.

Operation

if 'fmul' then
    FRT <- (FRA) * (FRC)
else if 'fmul.' then
    FRT <- (FRA) * (FRC)

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.