https://instructionsets.com/changes/ What has been added and fixed on instructionsets.com, the CPU and GPU instruction set reference. en Sun, 27 Sep 2026 00:00:00 +0000 https://instructionsets.com/notes/checking-the-gpu-decoder/ https://instructionsets.com/changes/#note-checking-the-gpu-decoder Sun, 27 Sep 2026 00:00:00 +0000 How the AMD GPU decoder was checked against LLVM's assembler, how far its zero wrong answers reach in each GPU generation, and why most instructions it sees get no answer rather than a guess. https://instructionsets.com/decode/ https://instructionsets.com/changes/#amdgpu-decoder Sun, 27 Sep 2026 00:00:00 +0000 The decoder now reads 32, 64 and 96-bit AMDGPU instructions for a GPU generation you choose, with every field broken out and register numbers where they can be read reliably. Paste bytes as LLVM prints them or dwords as llvm-objdump does. Checked against LLVM's own assembler tests: 25,923 instructions decoded, none to the wrong instruction. https://instructionsets.com/search/ https://instructionsets.com/changes/#address-bar-search Sun, 27 Sep 2026 00:00:00 +0000 Add instructionsets.com as a search engine and type an instruction straight into the address bar. A single exact match opens its page, and anything else is listed in full. Pressing Enter in any search box on the site now shows every result instead of only the first ten. https://instructionsets.com/changes/ https://instructionsets.com/changes/#whats-new-feed Sun, 27 Sep 2026 00:00:00 +0000 Changes to the site are listed here and published as an RSS feed, so a feed reader can tell you when something is added or fixed. https://instructionsets.com/powerisa/rlwinm/ https://instructionsets.com/changes/#powerisa-extended-mnemonics Sun, 27 Sep 2026 00:00:00 +0000 69 PowerISA pages printed blank cells in their Extended Mnemonics table. Every form is shown now, and where the source gives no equivalent instruction the page says so rather than leaving a gap. https://instructionsets.com/notes/measuring-the-reference/ https://instructionsets.com/changes/#note-measuring-the-reference Sun, 27 Sep 2026 00:00:00 +0000 How the accuracy of this reference was measured against its own vendor specifications, the 18 wrong RISC-V encodings that turned up, and the four times the audit itself was the problem. https://instructionsets.com/contact/ https://instructionsets.com/changes/#contact Tue, 22 Sep 2026 00:00:00 +0000 Report an error, ask a question or suggest something from the Contact page. The form opens your own email app with the message ready to send. https://instructionsets.com/amdgpu/v_cmp_lt_f32/ https://instructionsets.com/changes/#vcc-operand-and-full-diagrams Tue, 22 Sep 2026 00:00:00 +0000 AMDGPU comparisons (v_cmp_) now list the vcc destination they write. Bit diagrams wrap instead of scrolling sideways, which had hidden part of most ARM diagrams on a desktop screen. https://instructionsets.com/amdgpu/v_add_f32/ https://instructionsets.com/changes/#amdgpu-bit-layouts Thu, 17 Sep 2026 00:00:00 +0000 Taken from AMD's machine-readable ISA specification, each checked by rebuilding one of AMD's own encoding identifiers from the instruction's opcode. Opcodes change between GPU generations, so each diagram names its generation and says where the others differ. https://instructionsets.com/amdgpu/buffer_atomic_add_u32/ https://instructionsets.com/changes/#amdgpu-operands Sun, 13 Sep 2026 00:00:00 +0000 Named and in order, with whether each is read or written, from AMD's machine-readable ISA specification. AMDGPU pages with no operand list went from 910 to 142. https://instructionsets.com/ https://instructionsets.com/changes/#interface-fixes Sun, 13 Sep 2026 00:00:00 +0000 Instruction pages no longer run wider than a phone screen, wide tables scroll inside their panel, Ctrl+K or / jumps to search, and table headers sort from the keyboard. https://instructionsets.com/compare/cpu/ https://instructionsets.com/changes/#comparisons Mon, 07 Sep 2026 00:00:00 +0000 19 comparisons of how x86, ARM, RISC-V and PowerISA each express the same operation, including where one has no instruction for it, and 9 of NVIDIA PTX against AMDGPU. https://instructionsets.com/decode/ https://instructionsets.com/changes/#decoder Wed, 02 Sep 2026 00:00:00 +0000 Paste a 32-bit ARM or RISC-V instruction word and get the instruction with every field broken out. It carries only the 908 encodings whose bit pattern rebuilds their own opcode, so it declines rather than guesses. https://instructionsets.com/data/ https://instructionsets.com/changes/#cc0-dataset Wed, 02 Sep 2026 00:00:00 +0000 Every instruction record on the site, as JSON and JSONL under CC0. Use it for anything: no permission and no attribution needed. https://instructionsets.com/data/ https://instructionsets.com/changes/#accuracy-audit Tue, 01 Sep 2026 00:00:00 +0000 A published audit of how well the data agrees with the vendor specifications. It found 18 wrong RISC-V encodings, which were fixed.