addsd

Add Scalar Double-Precision

ADDSD xmm1, xmm2/m64

Adds the low 64-bit double from source to destination.

Details

The Add Scalar Double-Precision instruction adds the low 64-bit double from source to destination.

Pseudocode Operation

DEST <- DEST + SRC
// Flags affected: OF, SF, ZF, AF, CF, PF

Example

ADDSD xmm1, xmm2/m64

Encoding

Binary Layout
F2
+0
0F
+1
58
+2
 
Format SSE2
Opcode F2 0F 58
Extension SSE2

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand