ARM Instructions
1,374 instructions - showing 100 per page, page 13 of 14 - click any row to view encoding, pseudocode, and full documentation.
How ARM compares to the other CPU architectures
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| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| vcls | VCLS<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Counts number of consecutive sign bits. |
| vclt | VCLT<c>.<dt> <Qd>, <Qn>, <Qm> | NEON Alias | NEON (SIMD) | Compares elements (<). Alias for VCGT with swapped operands. |
| vclz | VCLZ<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Counts number of consecutive zeros. |
| vcmla | VCMLA<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> | NEON Complex | NEON (Complex) | Complex integer multiply-accumulate with rotation. |
| vcmp | VCMP<c>.F32 <Sd>, #0.0 | VFP Compare | VFP (Float) | Compares a floating-point value with #0.0. |
| vcmp | VCMP<c>.F64 <Dd>, <Dm> | VFP Compare | VFP (Float) | Compares two double-precision values. |
| vcmp | VCMP<c>.F32 <Sd>, <Sm> | VFP Compare | VFP (Float) | Compares two floating-point values. |
| vcmpe | VCMPE<c>.F32 <Sd>, <Sm> | VFP Compare | VFP (Float) | Compares values and raises exception on NaN. |
| vcnt | VCNT<c>.8 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Population count (number of 1s) per byte. |
| vcvt | VCVT<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits> | VFP Convert | VFP (Float) | Converts between floating-point and fixed-point. |
| vcvt | VCVT<c>.<Td>.<Tm> <Sd>, <Sm> | VFP Convert | VFP (Float) | Converts float to signed/unsigned integer. |
| vcvta | VCVTA<c>.<dt>.F64 <Sd>, <Dm> | VFP Convert | VFP (Float) | Converts double to integer, rounding to nearest. |
| vcvta | VCVTA<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding to nearest. |
| vcvtb | VCVTB<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Bottom half). |
| vcvtm | VCVTM<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding towards -Inf (Floor). |
| vcvtn | VCVTN<c>.<dt>.F64 <Sd>, <Dm> | VFP Convert | VFP (Float) | Converts double to integer, rounding to nearest even. |
| vcvtn | VCVTN<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding to nearest even. |
| vcvtp | VCVTP<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding towards +Inf (Ceil). |
| vcvtt | VCVTT<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Top half). |
| vdiv | VDIV<c>.F64 <Dd>, <Dn>, <Dm> | VFP Arith | VFP (Float) | Divides two double-precision registers. |
| vdiv | VDIV<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Divides two floating-point values. |
| vdot | VDOT<c>.BF16 <Qd>, <Qn>, <Qm> | NEON BFloat16 | NEON (BFloat16) | BFloat16 dot product to float32 accumulator. |
| vdup | VDUP<c>.<dt> <Qd>, <Dm[x]> | NEON Scalar | NEON (SIMD) | Duplicates a scalar value to all lanes of a vector. |
| veor | VEOR<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise XOR of two vectors. |
| vext | VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm> | NEON Extract | NEON (SIMD) | Extracts a new vector from a pair of vectors (Sliding window). |
| vfma | VFMA<c>.F64 <Qd>, <Qn>, <Qm> | VFP Arith | VFPv4 (Float) | Fused multiply-add (Double). |
| vfma | VFMA<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | VFPv4 (SIMD) | Computes Vd = Vd + (Vn * Vm) with single rounding. |
| vfms | VFMS<c>.F64 <Qd>, <Qn>, <Qm> | VFP Arith | VFPv4 (Float) | Fused multiply-subtract (Double). |
| vfms | VFMS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | VFPv4 (SIMD) | Computes Vd = Vd - (Vn * Vm) with single rounding. |
| vfnma | VFNMA<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFPv4 (Float) | Computes Vd = Vd - (Vn * Vm). |
| vfnms | VFNMS<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFPv4 (Float) | Computes Vd = -Vd + (Vn * Vm). |
| vhadd | VHADD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Add elements and shift right by 1 (Average). |
| vhsub | VHSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtract elements and shift right by 1. |
| vjcvt | VJCVT<c>.S32.F64 <Sd>, <Dm> | VFP Convert | VFP (JS) | Converts double to signed 32-bit integer (JS semantics). |
| vld1 | VLD1<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | Loads vector data from memory (interleaved or sequential). |
| vld2 | VLD2<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | De-interleaves 2 streams of data while loading. |
| vld3 | VLD3<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | Loads three-element structures (e.g., RGB) and de-interleaves them into three registers. |
| vld4 | VLD4<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | Loads four-element structures (e.g., RGBA) and de-interleaves them into four registers. |
| vldm | VLDM<c><mode> <Rn>{!}, <list> | VFP Load Multiple | VFP (Float) | Loads multiple VFP registers from memory. |
| vldr | VLDR<c> <Sd>, [<Rn>, #+/-<imm>] | VFP Load | VFP (Float) | Loads a floating-point register from memory. |
| vmax | VMAX<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Selects maximum value from elements. |
| vmaxnm | VMAXNM<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Returns larger value, handling NaNs per IEEE 754-2008. |
| vmaxnm | VMAXNM<c>.F64 <Dd>, <Dn>, <Dm> | VFP Misc | VFP (Float) | Returns larger double-precision value, handling NaNs. |
| vmin | VMIN<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Selects minimum value from elements. |
| vminnm | VMINNM<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Returns smaller value, handling NaNs per IEEE 754-2008. |
| vminnm | VMINNM<c>.F64 <Dd>, <Dn>, <Dm> | VFP Misc | VFP (Float) | Returns smaller double-precision value, handling NaNs. |
| vmla | VMLA<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Sd = Sd + (Sn * Sm). |
| vmla | VMLA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies and adds to accumulator. |
| vmls | VMLS<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Sd = Sd - (Sn * Sm). |
| vmls | VMLS<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies and subtracts from accumulator. |
| vmmla | VMMLA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (MatMul) | Matrix multiply-accumulate (BFloat16/Int8). |
| vmov | VMOV<c>.F64 <Dd>, <Dm> | VFP Move | VFP (Float) | Moves data between Double registers. |
| vmov | VMOV<c> <Rt>, <Rt2>, <Dm> | VFP Transfer | VFP (Float) | Moves a Double register to/from two Core registers. |
| vmov | VMOV<c>.F32 <Sd>, <Sm> | VFP Move | VFP (Float) | Moves data between VFP registers. |
| vmov | VMOV<c> <Sn>, <Rt> | VFP Transfer | VFP (Float) | Moves data between Core registers (R) and VFP registers (S). |
| vmov | VMOV<c>.<dt> <Qd>, #<imm> | NEON Imm | NEON (SIMD) | Moves immediate value into vector. |
| vmovl | VMOVL<c>.<dt> <Qd>, <Dm> | NEON 2-Reg | NEON (SIMD) | Copies N-bit elements to 2N-bit elements (Widening). |
| vmovn | VMOVN<c>.<dt> <Dd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Copies 2N-bit elements to N-bit elements (Narrowing). |
| vmrs | VMRS<c> <Rt>, <spec_reg> | VFP System | VFP (System) | Reads a VFP system register (like FPSCR). |
| vmsr | VMSR<c> <spec_reg>, <Rt> | VFP System | VFP (System) | Writes to a VFP system register. |
| vmul | VMUL<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Multiplies two floating-point values. |
| vmul | VMUL<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies elements. |
| vmull | VMULL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies N-bit elements producing 2N-bit results. |
| vmvn | VMVN<c> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Moves bitwise inverse of immediate/register. |
| vneg | VNEG<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Negates double-precision register. |
| vneg | VNEG<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Negates the value. |
| vneg | VNEG<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Negates integer/float elements. |
| vnmul | VNMUL<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Sd = -(Sn * Sm). |
| vorn | VORN<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise OR with NOT (Vd = Vn | ~Vm). |
| vorr | VORR<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise OR of two vectors. |
| vpadal | VPADAL<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Adds adjacent pairs and accumulates into wide destination. |
| vpadd | VPADD<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Adds adjacent pairs of elements. |
| vpaddl | VPADDL<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Adds adjacent pairs and produces wide result. |
| vpmax | VPMAX<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Maximum of adjacent pairs. |
| vpmin | VPMIN<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Minimum of adjacent pairs. |
| vpop | VPOP <list> | VFP Load Multiple | VFP (Float) | Pops VFP registers from the stack (Alias for VLDMIA SP!). |
| vpush | VPUSH <list> | VFP Store Multiple | VFP (Float) | Pushes VFP registers to the stack (Alias for VSTMDB SP!). |
| vqadd | VQADD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds elements with saturation. |
| vqdmlal | VQDMLAL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies, doubles, saturates, and adds to accumulator (High precision DSP). |
| vqdmlsl | VQDMLSL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies, doubles, saturates, and subtracts from accumulator. |
| vqdmulh | VQDMULH<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies, doubles, saturates, and keeps high half. |
| vqdmull | VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies narrow elements, doubles, and saturates into wide elements. |
| vqrdmulh | VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Fixed-point multiply with rounding and saturation. |
| vqrshl | VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Shifts left with saturation and rounding. |
| vqrshrn | VQRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right, saturates, rounds, and narrows. |
| vqshl | VQSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Shifts left with saturation based on register. |
| vqshl | VQSHL<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts left with saturation based on immediate. |
| vqshlu | VQSHLU<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts signed elements left, saturating to unsigned result. |
| vqshr | VQSHR<c>.U<size> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right with saturation (Unsigned). |
| vqshrn | VQSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right, saturates, and narrows. |
| vqsub | VQSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts elements with saturation. |
| vraddhn | VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds wide elements, rounds, and returns high narrow half. |
| vrecpe | VRECPE<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Estimates reciprocal (1/x). |
| vrecps | VRECPS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Newton-Raphson step for reciprocal refinement: (2 - Vn * Vm). |
| vrev16 | VREV16<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Reverses bytes within 16-bit halfwords. |
| vrev32 | VREV32<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Reverses elements within 32-bit words. |
| vrev64 | VREV64<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Reverses elements within 64-bit doublewords. |
| vrinta | VRINTA<c>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Rounds float to integral float (Nearest). |
| vrintm | VRINTM<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float towards Minus Infinity (Floor). |
| vrintm | VRINTM<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Rounds double towards Minus Infinity (Floor). |