ARM Instructions
1,374 instructions - showing 74 per page, page 14 of 14 - click any row to view encoding, pseudocode, and full documentation.
How ARM compares to the other CPU architectures
Decode a ARM instruction word
Download this data (public domain)
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| vrintn | VRINTN<c>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Rounds float to integral float (Nearest Even). |
| vrintp | VRINTP<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float towards Plus Infinity (Ceil). |
| vrintp | VRINTP<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Rounds double towards Plus Infinity (Ceil). |
| vrintr | VRINTR<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float to integral float using FPSCR rounding mode. |
| vrintx | VRINTX<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float to integral float, raising Inexact exception. |
| vrintz | VRINTZ<c>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Rounds float to integral float (Towards Zero). |
| vrshl | VRSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Shifts left with rounding based on a register value. |
| vrshr | VRSHR<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right with rounding based on immediate. |
| vrshrn | VRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right, rounds, and narrows (2N -> N bits). |
| vrsqrte | VRSQRTE<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Estimates reciprocal square root (1/sqrt(x)). |
| vrsqrts | VRSQRTS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2. |
| vrsra | VRSRA<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right with rounding and adds to accumulator. |
| vrsubhn | VRSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts wide elements, rounds, and returns high narrow half. |
| vsel | VSEL<cond>.F32 <Sd>, <Sn>, <Sm> | VFP Misc | VFP (Float) | Selects elements from Dn or Dm based on condition flags (predicated VFP). |
| vsel | VSEL<cond>.F64 <Dd>, <Dn>, <Dm> | VFP Misc | VFP (Float) | Selects between two double-precision registers based on flags. |
| vshl | VSHL<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts elements left. |
| vshr | VSHR<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts elements right. |
| vshrn | VSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right and narrows result. |
| vsli | VSLI<c>.<size> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts bits left and inserts into destination (merging). |
| vsmmla | VSMMLA<c>.S8 <Qd>, <Qn>, <Qm> | NEON MatMul | NEON (MatMul) | Matrix multiply-accumulate (Signed Int8). |
| vsqrt | VSQRT<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Square root of double-precision register. |
| vsqrt | VSQRT<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Calculates square root. |
| vsra | VSRA<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts elements right and adds to the destination accumulator. |
| vsri | VSRI<c>.<size> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts bits right and inserts into destination. |
| vst1 | VST1<c>.<size> <list>, [<Rn>]{!} | NEON Store | NEON (SIMD) | Stores vector data to memory. |
| vst3 | VST3<c>.<size> <list>, [<Rn>]{!} | NEON Store | NEON (SIMD) | Interleaves and stores three registers into memory (e.g., RGB). |
| vst4 | VST4<c>.<size> <list>, [<Rn>]{!} | NEON Store | NEON (SIMD) | Interleaves and stores four registers into memory (e.g., RGBA). |
| vstm | VSTM<c><mode> <Rn>{!}, <list> | VFP Store Multiple | VFP (Float) | Stores multiple VFP registers to memory. |
| vstr | VSTR<c> <Sd>, [<Rn>, #+/-<imm>] | VFP Store | VFP (Float) | Stores a floating-point register to memory. |
| vsub | VSUB<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Subtracts two floating-point values. |
| vsub | VSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts integer elements. |
| vsubhn | VSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts wide elements and returns high narrow half. |
| vswp | VSWP<c> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Swaps the contents of two vectors. |
| vtbl | VTBL<c>.8 <Dd>, <list>, <Dm> | NEON Table | NEON (SIMD) | Look up elements in a vector table. |
| vtbx | VTBX<c>.8 <Dd>, <list>, <Dm> | NEON Table | NEON (SIMD) | Inserts elements into a vector using a table lookup. |
| vtrn | VTRN<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Transposes elements of two vectors. |
| vtst | VTST<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Tests if any bits match (Vd = (Vn & Vm) != 0). |
| vummla | VUMMLA<c>.U8 <Qd>, <Qn>, <Qm> | NEON MatMul | NEON (MatMul) | Matrix multiply-accumulate (Unsigned Int8). |
| vusdot | VUSDOT<c>.S8 <Qd>, <Qn>, <Qm> | NEON DotProd | NEON (DotProd) | Dot product of unsigned (src1) and signed (src2) bytes. |
| vusmmla | VUSMMLA<c>.S8 <Qd>, <Qn>, <Qm> | NEON MatMul | NEON (MatMul) | Matrix multiply-accumulate (Unsigned x Signed Int8). |
| vuzp | VUZP<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | De-interleaves vectors. |
| vzip | VZIP<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Interleaves vectors. |
| wfe | WFE | System Alias | Base | Puts the processor into a low-power state until an event occurs. |
| wfe | WFE | System Hint | A32 (Base) | Enters low-power state until an event occurs. |
| wfe | WFE | Thumb System | T32 (Base) | Wait for event (Thumb). |
| wfet | WFET <Wn> | System | Base (v8.7) | Waits for an event or a timeout (using a counter). |
| wfi | WFI | System Alias | Base | Puts the processor into a low-power state until an interrupt occurs. |
| wfi | WFI | System Hint | A32 (Base) | Enters low-power state until an interrupt occurs. |
| wfi | WFI | Thumb System | T32 (Base) | Wait for interrupt (Thumb). |
| wfit | WFIT <Wn> | System | Base (v8.7) | Waits for an interrupt or a timeout. |
| whilege | WHILEGE <Pd>.<T>, <R><n>, <R><m> | SVE2 | SVE2 | While Greater or Equal (Extended) |
| whilegt | WHILEGT <Pd>.<T>, <R><n>, <R><m> | SVE2 | SVE2 | While Greater Than (Extended) |
| whilehi | WHILEHI <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn > Xm). |
| whilehs | WHILEHS <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn >= Xm). |
| whilele | WHILELE <Pd>.<T>, <Xn>, <Xm> | SVE Compare Scalar | SVE | Generates a predicate based on loop counter (while Xn <= Xm). |
| whilelo | WHILELO <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn < Xm). |
| whilels | WHILELS <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn <= Xm). |
| whilelt | WHILELT <Pd>.<T>, <Xn>, <Xm> | SVE Compare Scalar | SVE | Generates a predicate based on a loop counter (while Xn < Xm). |
| whilerw | WHILERW <Pd>.<T>, <Xn>, <Xm> | SVE2 Predicate | SVE2 | Generates a predicate for concurrent read/write loop iterations. |
| whilewr | WHILEWR <Pd>.<T>, <Xn>, <Xm> | SVE2 Predicate | SVE2 | Generates a predicate for concurrent write/read loop iterations. |
| wrffr | WRFFR <Pn>.B | SVE | SVE | Write First-Fault Register. |
| xar | XAR <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<const> | SVE2 Bitwise | SVE2 | Performs XOR followed by a right rotation (used in SHA-3/SM3). |
| xpacd | XPACD <Xd> | Data Processing | PAC (Security) | Removes the PAC signature from a data pointer. |
| xpaci | XPACI <Xd> | Data Processing | PAC (Security) | Removes the PAC signature from an instruction pointer. |
| xpaclri | XPACLRI | System | PAC (Security) | Removes the pointer authentication code from an instruction address. |
| xtn | XTN <Vd>.<Tb>, <Vn>.<Ta> | SIMD Shift Imm | NEON (SIMD) | Reads elements, narrows them, and writes to lower half of destination. |
| yield | YIELD | System Alias | Base | Hints that the current thread is performing a spin-wait loop. |
| yield | YIELD | System Hint | A32 (Base) | Hints that the task is performing a spin-wait. |
| yield | YIELD | Thumb System | T32 (Base) | Yield hint (Thumb). |
| zero | ZERO { {<mask>} } | SME | SME | Zero a list of 64-bit element tiles. |
| zip1 | ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Interleaves the lower halves of two vectors. |
| zip1 | ZIP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves elements from the lower halves. |
| zip2 | ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Interleaves the upper halves of two vectors. |
| zip2 | ZIP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves elements from the upper halves. |