PowerISA Instructions
1187 instructions - showing 100 per page, page 7 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| tlbie | tlbie RB, RS | X-form | Privileged | Invalidates a TLB entry corresponding to the address in RB. |
| tlbiel | tlbiel RS, RIC, PRS, effR | X-form | Privileged | Invalidates a TLB entry on the current processor only. |
| tlbilx | tlbilx T, RA, RB | X-form | Embedded | Invalidates TLB entries on the local processor based on Process ID (PID). |
| tlbivax | tlbivax RA, RB | X-form | Embedded | Invalidates a TLB entry by virtual address. |
| tlbre | tlbre | X-form | Embedded | Reads a TLB entry into MAS registers. |
| tlbsx | tlbsx RA, RB | X-form | Embedded | Searches the TLB for an address. |
| tlbsync | tlbsync | X-form | Privileged | Provides an ordering function for the effects of all tlbie instructions executed by the thread executing the tlbsync instruction. |
| tlbwe | tlbwe | X-form | Embedded | Writes a TLB entry from MAS registers. |
| trap | trap | Pseudo | Base | Unconditional trap. Forces an exception. (Encoded as tw 31, 0, 0). |
| trechkpt | trechkpt | X-form | Transactional Memory | Updates the transaction checkpoint. |
| tresume | tresume. | X-form | Transactional Memory | Resumes a suspended transaction. |
| tsr | tsr L | X-form | Transactional Memory | Suspends or resumes a transaction based on L. |
| tsuspend | tsuspend. | X-form | Transactional Memory | Suspends the current transaction. |
| tw | tw TO, RA, RB | X-form | Base | Traps if condition (comparison of words) is met. |
| twi | twi TO, RA, SIM | D-form | Base | Compares the contents of register RA with an immediate value and invokes the system trap handler if any specified condition is met. |
| urfid | urfid | XL-form | Privileged | Returns from an ultravisor interrupt. |
| vabsdub | vabsdub vD, vA, vB | VA-form | VMX (AltiVec) | Returns the absolute value of the difference of integer values in byte elements. |
| vabsduh | vabsduh vD, vA, vB | VA-form | VMX (AltiVec) | Computes |A - B| for halfwords. |
| vabsduw | vabsduw vD, vA, vB | VA-form | VMX (AltiVec) | Calculates the absolute difference of unsigned words from two vector registers and stores the result in another vector register. |
| vaddcuq | vaddcuq vD, vA, vB | VX-form | VMX (AltiVec) | Adds the contents of two vector registers and writes the carry-out to another register. |
| vaddcuw | vaddcuw vD, vA, vB | VX-form | VMX (AltiVec) | Adds the contents of two vector registers and writes the carry-out to another vector register. |
| vaddfp | vaddfp vD, vA, vB | VA-form | VMX (AltiVec) | Adds the contents of two vector registers and places the result in another vector register. |
| vaddsbs | vaddsbs vD, vA, vB | VX-form | VMX (AltiVec) | Adds 16 signed bytes with saturation (-128..127). |
| vaddshs | vaddshs vD, vA, vB | VX-form | VMX (AltiVec) | Adds the contents of two vector registers and saturates the result if it overflows. |
| vaddsws | vaddsws vD, vA, vB | VX-form | VMX (AltiVec) | Adds 4 signed words with saturation. |
| vaddubm | vaddubm vD, vA, vB | VX-form | VMX (AltiVec) | Adds the contents of two vector registers and updates the result in another vector register, modulo operation for bytes. |
| vaddubs | vaddubs vD, vA, vB | VX-form | VMX (AltiVec) | Adds the contents of two vector registers and saturates the result if it overflows. |
| vaddudm | vaddudm vD, vA, vB | VX-form | VMX (AltiVec) | Adds 2 doublewords modulo 2^64. |
| vadduhm | vadduhm vD, vA, vB | VX-form | VMX (AltiVec) | Adds 8 halfwords modulo 65536. |
| vadduhs | vadduhs vD, vA, vB | VX-form | VMX (AltiVec) | Adds the contents of two vector registers and saturates the result. |
| vadduqm | vadduqm vD, vA, vB | VA-form | VMX (AltiVec) | Adds the contents of two vector registers and updates the destination register with the result modulo 2^128. |
| vadduwm | vadduwm vD, vA, vB | VX-form | VMX (AltiVec) | Adds 4 words modulo 2^32. |
| vadduws | vadduws vD, vA, vB | VX-form | VMX (AltiVec) | Adds the contents of two vector registers and saturates the result if it exceeds 32 bits. |
| vand | vand vD, vA, vB | VX-form | VMX (AltiVec) | Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register. |
| vandc | vandc vD, vA, vB | VX-form | VMX (AltiVec) | Bitwise AND of vA with the ones' complement of vB (vA & ~vB). |
| vavgsb | vavgsb vD, vA, vB | VA-form | VMX (AltiVec) | Performs a signed byte-wise average of two vector registers and stores the result in another vector register. |
| vavgsh | vavgsh vD, vA, vB | VA-form | VMX (AltiVec) | Performs a signed halfword average operation on vector elements. |
| vavgsw | vavgsw vD, vA, vB | VA-form | VMX (AltiVec) | Performs a vector average of signed words from two source vectors and stores the result in a destination vector. |
| vavgub | vavgub vD, vA, vB | VA-form | VMX (AltiVec) | Computes (a+b+1)/2 for bytes. |
| vavguh | vavguh vD, vA, vB | VA-form | VMX (AltiVec) | Computes (a+b+1)/2 for halfwords. |
| vavguw | vavguw vD, vA, vB | VA-form | VMX (AltiVec) | Computes (a+b+1)/2 for words. |
| vbcdadd | vbcdadd vD, vA, vB, PS | VX-form | Vector Crypto | Adds two BCD (Binary Coded Decimal) vectors. |
| vbpermd | vbpermd VRT,VRA,VRB | VX-form | VMX (AltiVec) | Performs a bit permute operation on doublewords of two vector registers and stores the result in another vector register. |
| vbpermq | vbpermq VRT,VRA,VRB | VX-form | VMX (AltiVec) | Performs a bit permutation on two vector registers and stores the result in another vector register. |
| vbrd | vbrd vD, vB | VX-form | VMX (AltiVec) | Reverses bytes within each doubleword. |
| vbrh | vbrh vD, vB | VX-form | VMX (AltiVec) | Reverses bytes within each halfword (Endian Swap). |
| vbrq | vbrq vD, vB | VX-form | VMX (AltiVec) | Reverses bytes within the entire 128-bit quadword. |
| vbrw | vbrw vD, vB | VX-form | VMX (AltiVec) | Reverses bytes within each word. |
| vcfsx | vcfsx vD, vB, UIM | VX-form | VMX (AltiVec) | Converts signed fixed-point values in a vector register to single-precision floating-point values. |
| vcfuged | vcfuged vD, vA, vB | VX-form | VMX (AltiVec) | Separates bits of source into two groups based on mask (Power10). |
| vcfux | vcfux vD, vB, UIM | VX-form | VMX (AltiVec) | Converts 4 unsigned 32-bit integers to floats. |
| vcipher | vcipher vD, vA, vB | VX-form | Vector Crypto | Performs one round of AES encryption (SubBytes, ShiftRows, MixColumns, AddRoundKey). |
| vcipherlast | vcipherlast vD, vA, vB | VX-form | Vector Crypto | Performs the final round of AES encryption (SubBytes, ShiftRows, AddRoundKey). No MixColumns. |
| vclrlb | vclrlb vD, vA, RB | VX-form | VMX (AltiVec) | Clears the leftmost bytes in a vector register based on the value in a general-purpose register. |
| vclrrb | vclrrb vD, vA, RB | VX-form | VMX (AltiVec) | Clears the N rightmost bytes of a vector. |
| vclzb | vclzb vD, vB | VX-form | VMX (AltiVec) | Counts the number of leading zero bits in each byte element of a vector register. |
| vclzd | vclzd vD, vB | VX-form | VMX (AltiVec) | Counts the number of leading zero bits in each doubleword element of a vector register. |
| vclzdm | vclzdm VRT, VRA, VRB | X-form | VMX (AltiVec) | Counts the number of leading zeros in each doubleword element of a vector, considering a mask. |
| vclzh | vclzh vD, vB | VX-form | VMX (AltiVec) | Counts leading zeros in each halfword. |
| vclzlsbb | vclzlsbb RA, vB | VX-form | VMX (AltiVec) | Counts the number of contiguous leading byte elements in VSR[VRB+32] having a zero least-significant bit. |
| vclzw | vclzw vD, vB | VX-form | VMX (AltiVec) | Counts the number of leading zero bits in each word element of a vector register. |
| vcmpbfp | vcmpbfp VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two VSRs word element by word and sets the target VSR if Rc=1. |
| vcmpbfp. | vcmpbfp. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two VSRs word element by word and sets the target VSR if Rc=1. |
| vcmpeqfp | vcmpeqfp VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares the elements of two vector registers for equality and stores the result in a third vector register. |
| vcmpeqfp. | vcmpeqfp. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares the elements of two vector registers for equality and stores the result in a third vector register. |
| vcmpequb | vcmpequb VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison. |
| vcmpequb. | vcmpequb. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two vector registers element by element as unsigned bytes and sets the target vector register based on the comparison. |
| vcmpequd | vcmpequd VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register. |
| vcmpequd. | vcmpequd. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register. |
| vcmpequh | vcmpequh VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s. |
| vcmpequh. | vcmpequh. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s. |
| vcmpequq | vcmpequq VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros. |
| vcmpequq. | vcmpequq. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros. |
| vcmpequw | vcmpequw VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s. |
| vcmpequw. | vcmpequw. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each word of two vector registers and sets the corresponding word in the target register to all 1s if they are equal, otherwise all 0s. |
| vcmpgefp | vcmpgefp vD, vA, vB | VC-form | VMX (AltiVec) | Compares 4 floats (A >= B). |
| vcmpgefp. | vcmpgefp. VRT, VRA, VRB | VC-form | Base | Compares the elements of two vector registers and sets the result in a third vector register based on whether each element is greater than or equal to the corresponding element in the other vector. |
| vcmpgtfp | vcmpgtfp VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector. |
| vcmpgtfp. | vcmpgtfp. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector. |
| vcmpgtsb | vcmpgtsb VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s. |
| vcmpgtsb. | vcmpgtsb. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each byte of two vector registers and sets the corresponding result byte to all 1s if the signed byte in the first source register is greater than the signed byte in the second source register, otherwise sets it to all 0s. |
| vcmpgtsd | vcmpgtsd VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two doublewords of signed integers and sets the result vector based on the comparison. |
| vcmpgtsd. | vcmpgtsd. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two doublewords of signed integers and sets the result vector based on the comparison. |
| vcmpgtsh | vcmpgtsh VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s. |
| vcmpgtsh. | vcmpgtsh. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each halfword of two vector registers and sets the corresponding result element to all 1s if the first operand is greater than the second, otherwise all 0s. |
| vcmpgtsq | vcmpgtsq VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two signed quadwords and sets the result based on whether the first is greater than the second. |
| vcmpgtsq. | vcmpgtsq. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares two signed quadwords and sets the result based on whether the first is greater than the second. |
| vcmpgtsw | vcmpgtsw VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s. |
| vcmpgtsw. | vcmpgtsw. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s. |
| vcmpgtub | vcmpgtub vD, vA, vB | VC-form | VMX (AltiVec) | Unsigned > comparison for 16 bytes. |
| vcmpgtud | vcmpgtud vD, vA, vB | VC-form | VMX (AltiVec) | Compares the contents of two vector registers and sets a result based on whether each element in the first register is greater than the corresponding element in the second register. |
| vcmpgtuh | vcmpgtuh vD, vA, vB | VC-form | VMX (AltiVec) | Unsigned > comparison for 8 halfwords. |
| vcmpgtuw | vcmpgtuw vD, vA, vB | VC-form | VMX (AltiVec) | Unsigned > comparison for 4 words. |
| vcmpneb | vcmpneb VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s. |
| vcmpneb. | vcmpneb. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each byte of two vector registers and sets the result register to all 1s if the bytes are not equal, otherwise all 0s. |
| vcmpneh | vcmpneh VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s. |
| vcmpneh. | vcmpneh. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares the contents of two vector registers and sets the result register to all 1s if the elements are not equal, otherwise all 0s. |
| vcmpnew | vcmpnew VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s. |
| vcmpnew. | vcmpnew. VRT,VRA,VRB | VC-form | VMX (AltiVec) | Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the words are not equal, otherwise to all 0s. |
| vcmpsq | vcmpsq BF,VRA,VRB | VX-form | VMX (AltiVec) | Compares the signed integer values in two vector registers and updates the condition register. |