PowerISA Instructions

1187 instructions - showing 100 per page, page 5 of 12 - click any row to view encoding, pseudocode, and full documentation.

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By extension → 100 instructions
Mnemonic ⇅ Syntax Format ⇅ Extension ⇅ Summary
mulchw mulchw RT, RA, RB XO-form Embedded Multiply bottom half of RA by top half of RB.
mulchwu mulchwu RT, RA, RB XO-form Embedded Unsigned Multiply Cross Halfword.
mulhd mulhd RT, RA, RB XO-form Base Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Signed).
mulhd. mulhd. RT,RA,RB XO-form Base Multiplies the contents of two registers and places the high-order 64 bits of the product into a target register.
mulhdu mulhdu RT, RA, RB XO-form Base Multiplies two 64-bit integers and returns the upper 64 bits of the 128-bit result (Unsigned).
mulhhw mulhhw RT, RA, RB XO-form Embedded Multiply top half of RA by top half of RB.
mulhhwu mulhhwu RT, RA, RB XO-form Embedded Unsigned Multiply High Halfword.
mulhw mulhw RT, RA, RB XO-form Base Multiplies two 32-bit integers and returns the upper 32 bits (Signed).
mulhwu mulhwu RT, RA, RB XO-form Base Multiplies two 32-bit integers and returns the upper 32 bits (Unsigned).
mulld mulld RT,RA,RB XO-form Base Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.
mulldo mulldo RT,RA,RB XO-form Base Multiplies the contents of two registers and places the low-order 64 bits of the product into a target register.
mullhw mullhw RT, RA, RB XO-form Embedded Multiply bottom half of RA by bottom half of RB.
mullhwu mullhwu RT, RA, RB XO-form Embedded Unsigned Multiply Low Halfword.
mulli mulli RT,RA,SI D-form Base Multiplies the contents of a register by an immediate value and places the low-order 32 bits of the product into another register.
mullw mullw RT, RA, RB XO-form Base Multiplies two 32-bit integers and stores the lower 32 bits of the 64-bit result.
nand nand RA, RS, RB X-form Base Bitwise NAND. RA = ~(RS & RB).
neg neg RT, RA XO-form Base Computes the two's complement negation of a register (0 - RT).
nmacchw nmacchw RT, RA, RB XO-form Embedded Negate product of cross halfwords and add to accumulator.
nmacchws nmacchws RT, RA, RB XO-form Embedded Negate product of cross halfwords and add to accumulator (Signed Saturation).
nmachhw nmachhw RT, RA, RB XO-form Embedded Negate product of high halfwords and add to accumulator.
nmachhws nmachhws RT, RA, RB XO-form Embedded Negate product of high halfwords and add to accumulator (Signed Saturation).
nmaclhw nmaclhw RT, RA, RB XO-form Embedded Negate product of low halfwords and add to accumulator.
nmaclhws nmaclhws RT, RA, RB XO-form Embedded Negate product of low halfwords and add to accumulator (Signed Saturation).
nop nop D-form Base Does nothing. (Alias for 'ori 0, 0, 0').
nor nor RA, RS, RB X-form Base Bitwise NOR. RA = ~(RS | RB).
not not Rx,Ry X-form Base Complements the contents of one register and places the result into another register.
not. not. Rx,Ry X-form Base Complements the contents of one register and places the result into another register.
or or RT,RA,RB X-form Base Performs a bitwise OR operation on the contents of two registers and places the result in a third register.
or. or. RT,RA,RB X-form Base Performs a bitwise OR operation on the contents of two registers and updates the condition register.
orc orc RA,RS,RB X-form Base Performs a bitwise OR operation between the contents of two registers and the complement of the third register.
orc. orc. RA,RS,RB X-form Base Performs a bitwise OR operation between the contents of two registers and the complement of the third register.
ori ori RT,RS,SImm D-form Base Performs a bitwise OR operation between the contents of a register and an immediate value, placing the result in another register.
oris oris RA, RS, UI D-form Base Performs a bitwise OR with a 16-bit immediate shifted left by 16 bits.
paddi paddi RT, RA, SI, R MLS:D-form Prefixed Adds 34-bit immediate.
paste paste RA, RB X-form Privileged Transfers data from the copy buffer to a specified memory location.
paste. paste. RA, RB X-form Privileged Paste operation that updates CR0 to indicate success/fail.
pdepd pdepd RA, RS, RB X-form Base Deposits bits from RS to RA under control of mask RB (Scalar).
pextd pextd RA, RS, RB X-form Base Extracts bits from a source register based on a mask and places them into the target register.
pla pla RT, label Pseudo Prefixed Pseudo-instruction for paddi with R=1. Loads the address of a label.
plbz plbz RT, D34(RA), R MLS:D-form Prefixed Loads a byte and zero-extends it, using a 34-bit offset.
pld pld RT, D34(RA), R MLS:D-form Prefixed Loads a 64-bit value from memory using a 34-bit immediate offset (PC-relative or absolute).
plfd plfd RT,RA,RB D-form Prefixed Loads a double-precision floating-point value from memory into a VSX register.
plh plh RT, D(RA), R MLS:D-form Prefixed Loads 16-bit halfword using 34-bit offset.
plha plha RT, D(RA), R MLS:D-form Prefixed Loads 16-bit halfword (Sign Extended) using 34-bit offset.
pli pli RT, SI34 MLS:D-form Prefixed Loads a 34-bit signed immediate into a register. (Replaces multiple 'lis/ori' instructions).
plq plq RTp, D(RA), R MLS:D-form Prefixed Loads 128 bits into two GPRs using a 34-bit offset.
plwa plwa RT, D(RA), R MLS:D-form Prefixed Loads 32-bit word (Sign Extended) using 34-bit offset.
plwz plwz RT, D34(RA), R MLS:D-form Prefixed Loads a 32-bit word and zero-extends it to 64 bits, using a 34-bit offset.
plxv plxv RT,RA,RB D-form Prefixed Loads a 128-bit VSX vector from memory into a VSX register using a prefixed instruction with a large displacement.
plxvp plxvp XT, D(RA), R 8LS:D-form Prefixed Loads a 256-bit vector pair with 34-bit offset.
pmxvbf16ger2 pmxvbf16ger2 AT, XA, XB, XMSK, YMSK MMIRR-form Prefixed Matrix Multiply Assist (MMA) instruction. Computes ACC <- ACC + (A * B) using BF16 inputs.
pmxvbf16ger2np pmxvbf16ger2np AT,XA,XB,XMSK,YMSK,PMSK MMIRR:XX3-form VSX Performs a masked vector operation with bfloat16 elements using negative multiplication and positive accumulation.
pmxvf16ger2np pmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK MMIRR:XX3-form VSX Performs a masked vector operation with negative multiplication and positive accumulation.
pmxvf16ger2pp pmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK MMIRR:XX3-form MMA Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.
pmxvf32gernp pmxvf32gernp AT,XA,XB,XMSK,YMSK MMIRR:XX3-form VSX Performs a masked vector operation with negative multiplication and positive accumulation.
pmxvf32gerpp pmxvf32gerpp MMIRR:XX3-form MMA Performs a prefixed masked VSX vector 32-bit floating-point GER rank-1 update with positive multiply and positive accumulate.
pmxvf64ger pmxvf64ger AT, XA, XB, XMSK, YMSK MMIRR-form Prefixed Masked version of Double-Precision MMA.
pmxvf64gernn pmxvf64gernn AT,XAp,XB,XMSK,YMSK MMIRR:XX3-form MMA Performs a prefixed masked VSX vector 64-bit floating-point GER (rank-1 update) with negative multiply and negative accumulate.
pmxvf64gernp pmxvf64gernp AT,XAp,XB,XMSK,YMSK MMIRR:XX3-form VSX Performs a masked vector floating-point operation with negative multiplication and positive accumulation.
pmxvi4ger8 pmxvi4ger8 AT, XA, XB, XMSK, YMSK MMIRR-form Prefixed Masked 4-bit integer matrix multiply.
pmxvi4ger8pp pmxvi4ger8pp AT, XA, XB, XMSK, YMSK MMIRR-form Prefixed Masked unsigned 4-bit integer matrix multiply.
pmxvi8ger4 pmxvi8ger4 AT, XA, XB, XMSK, YMSK MMIRR-form Prefixed Masked version of 8-bit integer MMA.
pmxvi8ger4pp pmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK MMIRR:XX3-form MMA Performs a prefixed masked VSX vector 8-bit signed/unsigned integer GER rank-4 update with positive multiply and positive accumulate, adding the result to the accumulator.
pnop pnop *-form Prefixed No operation is performed.
popcntb popcntb RA,RS X-form Base Counts the number of one bits in each byte of a register.
popcntd popcntd RA, RS X-form Base Counts the number of set bits (1s) in a 64-bit register.
popcntw popcntw RA, RS X-form Base Counts the number of set bits (1s) in the lower 32 bits of a register.
prtyd prtyd RA, RS X-form Base Calculates parity of a doubleword (Scalar).
prtyw prtyw RA, RS X-form Base Calculates parity of a word (Scalar).
ps_add ps_add FRT, FRA, FRB A-form VMX (AltiVec) Adds two paired singles.
ps_madd ps_madd FRT, FRA, FRC, FRB A-form VMX (AltiVec) Multiply-Add on paired singles.
ps_mul ps_mul FRT, FRA, FRC A-form VMX (AltiVec) Multiplies two paired singles.
ps_sub ps_sub FRT, FRA, FRB A-form VMX (AltiVec) Subtracts two paired singles.
psq_l psq_l FRT, D(RA), W, I X-form VMX (AltiVec) Loads a paired single from memory (Embedded/Legacy).
psq_st psq_st FRS, D(RA), W, I X-form VMX (AltiVec) Stores a paired single to memory (Embedded/Legacy).
pstb pstb RS, D(RA), R MLS:D-form Prefixed Stores byte using 34-bit offset.
pstfd pstfd FRT,RA,RB MLS:D-form Prefixed Stores a double-precision floating-point value from a register to memory.
pstfs pstfs FRT,RA,RB MLS:D-form Floating-Point Stores a single-precision floating-point value from a register to memory.
psth psth RS, D(RA), R MLS:D-form Prefixed Stores halfword using 34-bit offset.
pstq pstq RSp, D(RA), R MLS:D-form Prefixed Stores 128 bits from two GPRs using a 34-bit offset.
pststd pststd RS, D34(RA), R MLS:D-form Prefixed Stores a 64-bit value to memory using a 34-bit immediate offset.
pstw pstw RS, D(RA), R MLS:D-form Prefixed Stores word using 34-bit offset.
pstxvp pstxvp XS, D(RA), R 8LS:D-form Prefixed Stores a 256-bit vector pair with 34-bit offset.
rfebb rfebb S XL-form Base Returns control to the address specified by EBBRR0:61 || 0b00 or 320 || EBBRR32:61 || 0b00, depending on MSRSF.
rfid rfid XL-form Privileged Returns from an interrupt handler. Restores PC from SRR0 and MSR from SRR1.
rfscv rfscv XL-form Privileged Returns from a vectored system call.
rldcr rldcr RT,RS,RB,ME MDS-form Base Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.
rldcr. rldcr. RT,RS,RB,ME MDS-form Base Rotates the contents of register RS left by a variable number of bits specified by (RB)58:63, and clears the rightmost bits.
rldic rldic RT,RA,RB,MB MD-form Base Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.
rldic. rldic. RT,RA,RB,MB MD-form Base Rotates a 64-bit register left, then clears bits based on a mask. 64-bit equivalent of rlwinm.
rldicl rldicl RA, RS, SH, MB MD-form Base Rotates the contents of a register left by a specified number of bits and clears higher-order bits.
rldicr rldicr RA, RS, SH, ME MD-form Base Rotates 64-bit RS left by SH, then clears the low-order bits (ME+1 to 63).
rldimi rldimi RA, RS, SH, MB MD-form Base Rotates 64-bit value and inserts into target under mask.
rlwimi rlwimi RA, RS, SH, MB, ME M-form Base Rotates a word left, then inserts bits into the target under a mask. Used for inserting bitfields.
rlwinm rlwinm RA,RS,SH,MB,ME M-form Base Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.
rlwinm. rlwinm. RA,RS,SH,MB,ME M-form Base Rotates the low-order 32 bits of a register left by a specified number of bit positions, generates a mask, and performs an AND operation.
rlwnm rlwnm RT,RS,RB,MB,ME M-form Base Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.
rlwnm. rlwnm. RT,RS,RB,MB,ME M-form Base Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.
sc sc LEV SC-form Base Provides the means by which a program can call upon the system to perform a service.
scv scv LEV SC-form Base Performs a system call to a fixed vector address (Faster than 'sc').