PowerISA Instructions

1187 instructions - showing 100 per page, page 4 of 12 - click any row to view encoding, pseudocode, and full documentation.

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Mnemonic ⇅ Syntax Format ⇅ Extension ⇅ Summary
lxsiwax lxsiwax XT, RA, RB XX1-form VSX Loads a word from memory into the left-most doubleword element of a VSR, sign-extends it to 64 bits, and aligns it.
lxsiwzx lxsiwzx XT, RA, RB XX1-form VSX Loads a word from memory and places it into the specified VSX register, zero-extending it.
lxssp lxssp RT,RA,RB XX2-form VSX Accesses a floating-point operand in single-precision format from storage, converts it to double-precision format, and loads it into a VSR.
lxsspx lxsspx XT,RA,RB X-form VSX Loads a single-precision floating-point value from memory and converts it to double-precision format in a VSX register.
lxv lxv XT, DQ(RA) DQ-form VSX Loads a 128-bit vector from memory (VSX aligned offset).
lxvb16x lxvb16x XT,RA,RB X-form VSX Loads a vector of 16 byte elements from memory into a VSX register.
lxvd2x lxvd2x XT, RA, RB XX1-form VSX Loads a 128-bit vector from memory into a VSX register. Does NOT require 16-byte alignment (unlike lvx).
lxvdsx lxvdsx XT, RA, RB X-form VSX Loads a doubleword from memory and splats it into two elements of a VSX vector register.
lxvh8x lxvh8x XT,RA,RB X-form VSX Loads a vector of 8 halfwords from memory into a VSX register.
lxvkq lxvkq XT,UIM X-form VSX Loads a special value into a VSX vector register.
lxvl lxvl XT, RA, RB XX1-form VSX Loads N bytes into a vector, where N is specified in a GPR.
lxvll lxvll XT,RA,RB X-form VSX Loads a variable-length vector from memory into a VSX register, left-justifying the data.
lxvp lxvp XT, DQ(RA) DQ-form VSX Loads a double quadword from memory into two VSX registers.
lxvpx lxvpx XTp,RA,RB X-form VSX Loads a vector from memory into two VSR registers.
lxvrbx lxvrbx XT,RA,RB X-form VSX Loads a byte from memory into the rightmost byte of a VSX vector register.
lxvrdx lxvrdx XT,RA,RB X-form VSX Loads a doubleword from memory into the rightmost element of a VSX vector register.
lxvrhx lxvrhx XT,RA,RB X-form VSX Loads a halfword from memory into the rightmost element of a VSX vector register.
lxvrwx lxvrwx XT,RA,RB X-form VSX Loads a word from memory into the rightmost word of a VSX vector register.
lxvw4x lxvw4x XT, RA, RB XX1-form VSX Loads four words into a vector (unaligned).
lxvwsx lxvwsx XT, RA, RB XX1-form VSX Loads a 32-bit word and replicates it across the vector.
lxvx lxvx XT,RA,RB X-form VSX Loads a quadword from memory into a VSX register.
macchw macchw RT, RA, RB XO-form Embedded Multiply bottom half of RA by top half of RB, add to RT.
macchws macchws RT, RA, RB XO-form Embedded Signed Multiply Accumulate Cross Halfword with Saturation.
macchwsu macchwsu RT, RA, RB XO-form Embedded Mixed Sign Multiply Accumulate Cross Halfword with Saturation.
macchwu macchwu RT, RA, RB XO-form Embedded Unsigned Multiply Accumulate Cross Halfword.
machhw machhw RT, RA, RB XO-form Embedded Multiply top half of RA by top half of RB, add to RT.
machhws machhws RT, RA, RB XO-form Embedded Signed Multiply Accumulate High Halfword with Saturation.
machhwsu machhwsu RT, RA, RB XO-form Embedded Mixed Sign Multiply Accumulate High Halfword with Saturation.
machhwu machhwu RT, RA, RB XO-form Embedded Unsigned Multiply Accumulate High Halfword.
maclhw maclhw RT, RA, RB XO-form Embedded Multiply bottom half of RA by bottom half of RB, add to RT.
maclhws maclhws RT, RA, RB XO-form Embedded Signed Multiply Accumulate Low Halfword with Saturation.
maclhwsu maclhwsu RT, RA, RB XO-form Embedded Mixed Sign Multiply Accumulate Low Halfword with Saturation.
maclhwu maclhwu RT, RA, RB XO-form Embedded Unsigned Multiply Accumulate Low Halfword.
maddhd maddhd RT,RA,RB,RC VA-form Base Multiplies two 64-bit operands and adds the result to a third 64-bit operand, placing the high-order 64 bits of the sum into a target register.
mcrf mcrf BF, BFA XL-form Base Copies the contents of one Condition Register field to another. Used to save comparison results.
mcrfs mcrfs BF, BFA X-form Floating-Point Moves a field from the Floating-Point Status and Control Register (FPSCR) to the Condition Register.
mcrxrx mcrxrx BF X-form Base Copies the contents of the XER register fields OV, OV32, CA, and CA32 to the specified condition register field.
mfbhrbe mfbhrbe RT, BHRBE X-form Base Reads a specific entry from the BHRB.
mfcr mfcr RT X-form Base Copies the entire 32-bit Condition Register into a General Purpose Register.
mfctr mfctr RT XFX-form Base Moves CTR to GPR. (Alias for 'mfspr RT, 9').
mfdcr mfdcr RT, DCRN XFX-form Embedded Reads an on-chip peripheral register (DCR).
mffs mffs FRT X-form Floating-Point Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.
mffs. mffs. FRT X-form Floating-Point Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.
mffscdrn mffscdrn FRT,FRB X-form Floating-Point Moves control bits from FPSCR to a register and sets the DRN field.
mffsl mffsl FRT X-form Floating-Point Moves the control and non-sticky status bits from the FPSCR to a general-purpose register.
mflr mflr RT XFX-form Base Moves LR to GPR. (Alias for 'mfspr RT, 8').
mfmsr mfmsr RT X-form Privileged Moves the contents of the Machine State Register (MSR) into a general-purpose register.
mfocrf mfocrf RT, FXM XFX-form Base Moves a single CR field to a GPR.
mfpmr mfpmr RT, PMRN X-form Embedded Reads a performance monitor register (Embedded).
mfpvr mfpvr RT X-form Privileged Reads the PVR (Processor ID).
mfspr mfspr RT, SPR XFX-form Base Moves the contents of a special purpose register into a general-purpose register.
mfsr mfsr RT, SR X-form Base Legacy 32-bit segment register read.
mfsrin mfsrin RT, RB X-form Base Indirect read of segment register using RB.
mftar mftar RT XFX-form Base Reads the TAR into a GPR.
mftb mftb RT,268 XFX-form Base Moves the contents of the Time Base Register (TBR) into a general-purpose register.
mftbu mftbu RT XFX-form Base Reads the upper 32 bits of the Timebase (32-bit implementations).
mfvsrd mfvsrd RA, XS XX1-form VSX Moves the contents of a doubleword element from a Vector-Scalar Register (VSR) to a General Purpose Register (GPR).
mfvsrld mfvsrld RA, XS XX1-form VSX Moves the lower doubleword of a vector register to a general-purpose register.
mfvsrwz mfvsrwz RA, XS XX1-form VSX Moves the contents of a word element from a vector-scalar register to a general-purpose register, zeroing the upper bits.
modsd modsd RT, RA, RB X-form Base Calculates remainder of signed doubleword division.
modsq modsq vD, vA, vB VX-form Base Computes remainder of 128-bit signed division.
modsw modsw RT, RA, RB X-form Base Calculates remainder of signed word division.
modud modud RT, RA, RB X-form Base Calculates remainder of unsigned doubleword division.
moduq moduq vD, vA, vB VX-form Base Computes remainder of 128-bit unsigned division.
moduw moduw RT, RA, RB X-form Base Calculates remainder of unsigned word division.
mr mr RA, RS X-form Base Copies contents of RS to RA. (Alias for 'or RA, RS, RS').
msgclr msgclr RB X-form Privileged Clears a pending doorbell interrupt (Inter-processor comms).
msgclrp msgclrp RB X-form Privileged Clears a privileged doorbell interrupt.
msgslp msgslp RB X-form Privileged Transitions the processor to a sleep state via message.
msgsnd msgsnd RB X-form Privileged Sends a doorbell interrupt to another processor.
msgsndp msgsndp RB X-form Privileged Sends a message to other threads on the same processor or sub-processor.
msgsndu msgsndu RB X-form Privileged Sends a message to other threads in the system.
msgsync msgsync X-form Privileged Provides an ordering function for stores relative to data accesses by other threads after a Directed Ultravisor Doorbell or Directed Hypervisor Doorbell interrupt.
msync msync X-form Embedded Synchronizes memory accesses (Alias for sync).
mtcrf mtcrf FXM, RS XFX-form Base Copies bits from a register into the Condition Register, updated only the fields specified by the mask (FXM).
mtctr mtctr RS XFX-form Base Moves GPR to CTR. (Alias for 'mtspr 9, RS').
mtdcr mtdcr DCRN, RS XFX-form Embedded Writes an on-chip peripheral register (DCR).
mtfsb0 mtfsb0 BT X-form Floating-Point Clears a specific bit in the FPSCR.
mtfsb1 mtfsb1 BT X-form Floating-Point Sets a specific bit in the FPSCR.
mtfsf mtfsf FLM,FRB,L,W XFL-form Floating-Point Moves the contents of a floating-point register into specified fields of the FPSCR.
mtfsf. mtfsf. FLM,FRB,L,W XFL-form Floating-Point Moves the contents of a floating-point register into specified fields of the FPSCR.
mtfsfi mtfsfi BF, U X-form Floating-Point Writes a 4-bit immediate to a specific FPSCR field.
mtlr mtlr RS XFX-form Base Moves GPR to LR. (Alias for 'mtspr 8, RS').
mtmsr mtmsr RS,L X-form Privileged Sets the Machine State Register (MSR) based on the contents of a source register and a control bit.
mtmsrd mtmsrd RS,L X-form Privileged Sets the Machine State Register (MSR) based on the contents of a source register and an L field.
mtocrf mtocrf FXM, RS XFX-form Base Moves a GPR field to a single CR field.
mtpmr mtpmr PMRN, RS X-form Embedded Writes a performance monitor register (Embedded).
mtspr mtspr SPR, RS XFX-form Base Copies a value from a general-purpose register to a system SPR (e.g., CTR, LR, XER).
mtsr mtsr SR, RS X-form Base Legacy 32-bit segment register write.
mtsrin mtsrin RS, RB X-form Base Indirect write of segment register using RB.
mttar mttar RS XFX-form Base Moves a GPR value to the TAR.
mtvscr mtvscr VRB VX-form VMX (AltiVec) Moves the contents of a vector register word into the VSCR.
mtvsrbm mtvsrbm VRT,RB VX-form VMX (AltiVec) Moves a byte mask from a GPR to a VSR.
mtvsrbmi mtvsrbmi VRT,bm XO-form Base Moves a bit mask immediate value into a vector scalar register, setting each byte element based on corresponding bits of the immediate.
mtvsrd mtvsrd XT, RA XX1-form VSX Moves 64 bits from a GPR to a VSR.
mtvsrdd mtvsrdd XT, RA, RB X-form VSX Moves the contents of two general-purpose registers into a vector-scalar register (VSR) as doublewords.
mtvsrqm mtvsrqm VRT,RB VX-form VMX (AltiVec) Moves a quadword mask from a general-purpose register to a vector scalar register.
mtvsrwa mtvsrwa XT, RA XX1-form VSX Moves the two's-complement integer in bits 32:63 of GPR[RA] to doubleword element 0 of VSR[XT], sign-extended to 64 bits.
mtvsrwm mtvsrwm VRT,RB VX-form VMX (AltiVec) Moves a word mask from a general-purpose register to a vector scalar register.
mtvsrws mtvsrws XT, RA XX1-form VSX Moves a 32-bit word from a GPR and replicates it across the vector.