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ARM Opcode Map

Reverse lookup instructions by their hexadecimal encoding.

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Opcode Mnemonic Syntax Format Name
0x00400090 umaal UMAAL<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Unsigned Multiply Accumulate Accumulate Long
0x9BA00000 umaddl UMADDL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Unsigned Multiply-Add Long
0x04090000 umax UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Unsigned Maximum
0x2E206400 umax UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Maximum
0x04092000 umaxv UMAXV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Unsigned Maximum Reduction
0x040B0000 umin UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Unsigned Minimum
0x2E206C00 umin UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Minimum
0x040B2000 uminv UMINV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Unsigned Minimum Reduction
0x2E31A800 uminv UMINV <V><d>, <Vn>.<T> SIMD Across Lane Vector Unsigned Minimum Across
0xFBE00000 umlal UMLAL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Unsigned Multiply Accumulate Long (Thumb)
0x00A00090 umlal UMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Unsigned Multiply Accumulate Long (A32)
0x2E208000 umlal UMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Multiply-Accumulate Long
0x6E80A400 ummla UMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Unsigned Integer Matrix Multiply-Accumulate (NEON)
0x9BA08000 umsubl UMSUBL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Unsigned Multiply-Subtract Long
0x9BC07C00 umulh UMULH <Xd>, <Xn>, <Xm> Data Processing Unsigned Multiply High
0xFBA00000 umull UMULL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Unsigned Multiply Long (Thumb)
0x00800090 umull UMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Unsigned Multiply Long (A32)
0x2E20C000 umull UMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Multiply Long
0x2E200C00 uqadd UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Saturating Add
0x06600F10 uqadd16 UQADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Add 16
0x06600F90 uqadd8 UQADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Add 8
0x2E202C00 uqsub UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Saturating Subtract
0x06600F70 uqsub16 UQSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Subtract 16
0x06600FF0 uqsub8 UQSUB8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Subtract 8
0x2E214800 uqxtn UQXTN <Vd>.<Tb>, <Vn>.<Ta> SIMD Shift Imm Unsigned Saturating Extract Narrow
0x0EA1C800 urecpe URECPE <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Unsigned Reciprocal Estimate
0x0780F010 usad8 USAD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Sum of Absolute Differences
0x07800010 usada8 USADA8<c> <Rd>, <Rn>, <Rm>, <Ra> SIMD Integer Unsigned Sum of Absolute Differences Accumulate
0x06E00010 usat USAT<c> <Rd>, #<imm>, <Rm> {, <shift>} Data Proc Unsigned Saturate (A32)
0x06E00F30 usat16 USAT16<c> <Rd>, #<imm>, <Rm> Data Proc Unsigned Saturate 16 (A32)
0x44807800 usdot USDOT<c>.S8 <Qd>, <Qn>, <Qm> NEON 3-Reg Unsigned Signed Dot Product (A32)
0x0E809C00 usdot USDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Unsigned-Signed Dot Product (NEON)
0x2F000400 ushr USHR <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Vector Unsigned Shift Right
0x4E80AC00 usmmla USMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Unsigned-Signed Matrix Multiply-Accumulate (NEON)
0x2F001400 usra USRA <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Unsigned Shift Right and Accumulate
0x06500F70 usub16 USUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Subtract 16 (A32)
0x2E202000 usubl USUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Subtract Long
0x05333800 uunpkhi UUNPKHI <Zd>.<T>, <Zn>.<Tb> SVE Permute SVE Unsigned Unpack High
0x05323800 uunpklo UUNPKLO <Zd>.<T>, <Zn>.<Tb> SVE Permute SVE Unsigned Unpack Low
0x06E00070 uxtab UXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Unsigned Extend and Add Byte
0x06C00070 uxtab16 UXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Unsigned Extend and Add Byte 16
0x06F00070 uxtah UXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Unsigned Extend and Add Halfword
0xB2C0 uxtb UXTB <Rd>, <Rm> Thumb Data Proc Unsigned Extend Byte (Thumb)
0x06EF0070 uxtb UXTB<c> <Rd>, <Rm> {, <rotation>} Data Proc Unsigned Extend Byte (A32)
0x06CF0070 uxtb16 UXTB16<c> <Rd>, <Rm> {, <rotation>} Data Proc Unsigned Extend Byte 16 (A32)
0xB280 uxth UXTH <Rd>, <Rm> Thumb Data Proc Unsigned Extend Halfword (Thumb)
0x06FF0070 uxth UXTH<c> <Rd>, <Rm> {, <rotation>} Data Proc Unsigned Extend Halfword (A32)
0x0E001800 uzp1 UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Unzip 1
0x05206800 uzp1 UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Unzip 1
0x0E005800 uzp2 UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Unzip 2
0x05206C00 uzp2 UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Unzip 2
0xF2000710 vaba VABA<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Difference and Accumulate
0xF2800500 vabal VABAL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Absolute Difference and Accumulate Long
0xF2000700 vabd VABD<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Difference
0xF2800700 vabdl VABDL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Absolute Difference Long
0x0EB00BC0 vabs VABS<c>.F64 <Dd>, <Dm> VFP Unary Vector Absolute Value (Double)
0x0EB00AC0 vabs VABS<c>.F32 <Sd>, <Sm> VFP Unary Vector Absolute Value (VFP)
0xF3B10300 vabs VABS<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Absolute Value
0xF3000E10 vacge VACGE<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Compare Greater or Equal
0xF3200E50 vacgt VACGT<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Compare Greater Than
0x0E300A00 vadd VADD<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Add (VFP)
0x0E300B00 vadd VADD<c>.F64 <Dd>, <Dn>, <Dm> VFP Arith Vector Add Double (VFP)
0xF2000800 vadd VADD<c>.I<size> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Add (Integer)
0xF2800400 vaddhn VADDHN<c>.<dt> <Dd>, <Qn>, <Qm> NEON 3-Reg Vector Add High Narrow
0xF2800000 vaddl VADDL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Add Long
0xF2800100 vaddw VADDW<c>.<dt> <Qd>, <Qn>, <Dm> NEON 3-Reg Vector Add Wide
0xF2000110 vand VAND<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Bitwise AND
0xF3B60640 vbfcvt VBFCVT<c>.BF16.F32 <Qd>, <Qm> NEON BFloat16 Vector Convert BFloat16 (A32)
0xFC000C40 vbfmmla VBFMMLA<c>.BF16 <Qd>, <Qn>, <Qm> NEON BFloat16 Vector BFloat16 Matrix Multiply (A32)
0xF2100110 vbic VBIC<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Bitwise Bit Clear
0xF3300110 vbif VBIF<c> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Bit Insert False
0xF3200110 vbit VBIT<c> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Bit Insert True
0xF3100110 vbsl VBSL<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Bit Select
0xFC800840 vcadd VCADD<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> NEON Complex Vector Complex Add (A32)
0xF3000850 vceq VCEQ<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Compare Equal
0xF2000310 vcge VCGE<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Compare Greater Than or Equal
0xF2000300 vcgt VCGT<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Compare Greater Than
0xF2000310 vcle VCLE<c>.<dt> <Qd>, <Qn>, <Qm> NEON Alias Vector Compare Less Than or Equal
0xF3B00440 vcls VCLS<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Count Leading Sign Bits
0xF2000300 vclt VCLT<c>.<dt> <Qd>, <Qn>, <Qm> NEON Alias Vector Compare Less Than
0xF3B004C0 vclz VCLZ<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Count Leading Zeros
0xFC200840 vcmla VCMLA<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> NEON Complex Vector Complex Multiply Accumulate (A32)
0x0EB50A40 vcmp VCMP<c>.F32 <Sd>, #0.0 VFP Compare Vector Compare Zero (VFP)
0x0EB40B40 vcmp VCMP<c>.F64 <Dd>, <Dm> VFP Compare Vector Compare (Double)
0x0EB40A40 vcmp VCMP<c>.F32 <Sd>, <Sm> VFP Compare Vector Compare (VFP)
0x0EB40AC0 vcmpe VCMPE<c>.F32 <Sd>, <Sm> VFP Compare Vector Compare Exception (VFP)
0xF3B00500 vcnt VCNT<c>.8 <Qd>, <Qm> NEON 2-Reg Vector Count Set Bits
0x0EBE0A40 vcvt VCVT<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits> VFP Convert Vector Convert (Fixed Point)
0x0EB80940 vcvt VCVT<c>.<Td>.<Tm> <Sd>, <Sm> VFP Convert Vector Convert (Float to Integer)
0xFEBC0B40 vcvta VCVTA<c>.<dt>.F64 <Sd>, <Dm> VFP Convert Vector Convert to Integer (Nearest, Double)
0xFEBC0A40 vcvta VCVTA<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Nearest)
0x0EB20A40 vcvtb VCVTB<c>.F16.F32 <Sd>, <Sm> VFP Convert Vector Convert Half-Precision (Bottom)
0xFEBF0A40 vcvtm VCVTM<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Minus Infinity)
0xFEBD0B40 vcvtn VCVTN<c>.<dt>.F64 <Sd>, <Dm> VFP Convert Vector Convert to Integer (Nearest Even, Double)
0xFEBD0A40 vcvtn VCVTN<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Nearest Even)
0xFEBE0A40 vcvtp VCVTP<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Plus Infinity)
0x0EB20AC0 vcvtt VCVTT<c>.F16.F32 <Sd>, <Sm> VFP Convert Vector Convert Half-Precision (Top)
0x0E800B00 vdiv VDIV<c>.F64 <Dd>, <Dn>, <Dm> VFP Arith Vector Divide (Double)
0x0E800A00 vdiv VDIV<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Divide (VFP)
0xFC000D40 vdot VDOT<c>.BF16 <Qd>, <Qn>, <Qm> NEON BFloat16 Vector BFloat16 Dot Product (A32)