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ARM Opcode Map

Reverse lookup instructions by their hexadecimal encoding.

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Opcode Mnemonic Syntax Format Name
0x04082000 smaxv SMAXV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Signed Maximum Reduction
0x0E30A800 smaxv SMAXV <V><d>, <Vn>.<T> SIMD Across Lane Vector Signed Maximum Across
0x01600070 smc SMC<c> #<imm> System Secure Monitor Call (A32)
0xF7F08000 smc SMC #<imm> Thumb System Secure Monitor Call (Thumb)
0x040A0000 smin SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Signed Minimum
0x0E206C00 smin SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Signed Minimum
0x040A2000 sminv SMINV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Signed Minimum Reduction
0x01000080 smlabb SMLABB<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Bottom x Bottom)
0x010000C0 smlabt SMLABT<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Bottom x Top)
0x07000010 smlad SMLAD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate Dual
0xFBC00000 smlal SMLAL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Signed Multiply Accumulate Long (Thumb)
0x0E208000 smlal SMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Signed Multiply-Accumulate Long
0x01400080 smlalbb SMLALBB<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Bottom x Bottom)
0x014000C0 smlalbt SMLALBT<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Bottom x Top)
0x07400010 smlald SMLALD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long Dual
0x014000A0 smlaltb SMLALTB<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Top x Bottom)
0x014000E0 smlaltt SMLALTT<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Top x Top)
0x010000A0 smlatb SMLATB<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Top x Bottom)
0x010000E0 smlatt SMLATT<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Top x Top)
0x01200080 smlawb SMLAWB<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Word x Bottom)
0x012000C0 smlawt SMLAWT<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Word x Top)
0x07000050 smlsd SMLSD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Subtract Dual
0x07400050 smlsld SMLSLD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Subtract Long Dual
0x4E80A400 smmla SMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Signed Integer Matrix Multiply-Accumulate (NEON)
0x07500010 smmla SMMLA{R}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Most Significant Word Multiply Accumulate
0x0750F010 smmul SMMUL{R}<c> <Rd>, <Rn>, <Rm> Multiply Signed Most Significant Word Multiply
0x9B208000 smsubl SMSUBL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Signed Multiply-Subtract Long
0x0700F010 smuad SMUAD{X}<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply Add Dual
0x01600080 smulbb SMULBB<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Bottom x Bottom)
0x016000C0 smulbt SMULBT<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Bottom x Top)
0x9B407C00 smulh SMULH <Xd>, <Xn>, <Xm> Data Processing Signed Multiply High
0xFB800000 smull SMULL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Signed Multiply Long (Thumb)
0x0E20C000 smull SMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Signed Multiply Long
0x016000A0 smultb SMULTB<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Top x Bottom)
0x016000E0 smultt SMULTT<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Top x Top)
0x012000A0 smulwb SMULWB<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Word x Bottom)
0x012000E0 smulwt SMULWT<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Word x Top)
0x0700F050 smusd SMUSD{X}<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply Subtract Dual
0x052C8000 splice SPLICE <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T> SVE Permute SVE Splice Vectors
0x0E200C00 sqadd SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Signed Saturating Add
0x0E202C00 sqsub SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Signed Saturating Subtract
0x0E214800 sqxtn SQXTN <Vd>.<Tb>, <Vn>.<Ta> SIMD Shift Imm Signed Saturating Extract Narrow
0x2F004400 sri SRI <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shift Right and Insert
0xF8CD0500 srs SRS<c> SP{!}, #<mode> System Store Return State
0x06A00010 ssat SSAT<c> <Rd>, #<imm>, <Rm> {, <shift>} Data Proc Signed Saturate (A32)
0x06A00F30 ssat16 SSAT16<c> <Rd>, #<imm>, <Rm> Data Proc Signed Saturate 16 (A32)
0xF57FF040 ssbb SSBB System Hint Speculative Store Bypass Barrier (A32)
0x0F000400 sshr SSHR <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Vector Signed Shift Right
0x0F001400 ssra SSRA <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Signed Shift Right and Accumulate
0x06100F70 ssub16 SSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Subtract 16 (A32)
0x0E202000 ssubl SSUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Signed Subtract Long
0x0D000000 st1 ST1 { <Vt>.<T>, ... }, [<Xn|SP>] SIMD Load/Store Store Multiple Single Elements
0xE4004000 st1b ST1B { <Zt>.B }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Bytes
0xE580A000 st1d ST1D { <Zt>.D }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Doublewords
0xE480E000 st1h ST1H { <Zt>.H }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Halfwords
0xE5408000 st1w ST1W { <Zt>.S }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Words
0xE5608000 st1w ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, SXTW #<shift>] SVE Scatter SVE Scatter Store Words (Vector Index)
0x0C008000 st2 ST2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] SIMD Load/Store Store Multiple 2-Element Structures
0xD9A00800 st2g ST2G <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag (Two Granules)
0x0C004000 st3 ST3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] SIMD Load/Store Store Multiple 3-Element Structures
0x0C000000 st4 ST4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] SIMD Load/Store Store Multiple 4-Element Structures
0xF83F9000 st64b ST64B <Xt>, [<Xn|SP>] Load/Store Single-copy Atomic 64-byte Store
0xF820B000 st64bv ST64BV <Ws>, <Xt>, [<Xn|SP>] Load/Store Single-copy Atomic 64-byte Store with Return
0xF820A000 st64bv0 ST64BV0 <Ws>, <Xt>, [<Xn|SP>] Load/Store Single-copy Atomic 64-byte Store with Return (Zero)
0x0D205E00 stc STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Store Coprocessor (A32)
0xFD000000 stc2 STC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Store Coprocessor 2 (A32)
0xD9200400 stg STG <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag
0xD9200800 stg STG <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag
0x69000000 stgp STGP <Xt>, <Xt2>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag and Pair
0x0180FC90 stl STL<c> <Rt>, [<Rn>] Load/Store Store Release (A32)
0x01800E90 stlex STLEX<c> <Rd>, <Rt>, [<Rn>] Load/Store Store Release Exclusive (A32)
0x01C00E90 stlexb STLEXB<c> <Rd>, <Rt>, [<Rn>] Store Excl Store Release Exclusive Byte (A32)
0x01A00E90 stlexd STLEXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] Store Excl Store Release Exclusive Double (A32)
0x01E00E90 stlexh STLEXH<c> <Rd>, <Rt>, [<Rn>] Store Excl Store Release Exclusive Halfword (A32)
0x889FFC00 stlr STLR <Wt>, [<Xn|SP>] Load/Store Store-Release Register
0x089FFC00 stlrb STLRB <Wt>, [<Xn|SP>] Load/Store Store-Release Register Byte
0x489FFC00 stlrh STLRH <Wt>, [<Xn|SP>] Load/Store Store-Release Register Halfword
0x8800FC00 stlxr STLXR <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store-Release Exclusive Register
0x0800FC00 stlxrb STLXRB <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store-Release Exclusive Register Byte
0x4800FC00 stlxrh STLXRH <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store-Release Exclusive Register Halfword
0xC000 stm STM <Rn>!, <registers> Thumb Store Multiple Store Multiple (Thumb)
0x08000000 stm STM<mode><c> <Rn>{!}, <registers> Store Multiple Store Multiple (A32)
0xE8800000 stm.w STM.W <Rn>{!}, <registers> Thumb Store Multiple Store Multiple (Wide)
0x28000000 stnp STNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair (Non-temporal)
0x2D000000 stp STP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair SIMD&FP Registers
0x29000000 stp STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair of Registers
0xA9000000 stp STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair of Registers (64-bit)
0xBD000000 str STR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] Load/Store Store SIMD&FP Register (Immediate)
0xB9000000 str STR <Wt>, [<Xn|SP>, #<pimm>] Load/Store Imm Store Register (Immediate)
0xB8200800 str STR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Store Register (Register)
0x04000000 str STR<c> <Rt>, [<Rn>, #+/-<imm>]{!} Load/Store Store Register (A32)
0xF8C00000 str.w STR.W <Rt>, [<Rn>, #<imm>] Thumb Store Store Register (Wide)
0x39000000 strb STRB <Wt>, [<Xn|SP>, #<pimm>] Load/Store Store Register Byte (Immediate)
0x38200800 strb STRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Store Register Byte (Register)
0xF8800000 strb.w STRB.W <Rt>, [<Rn>, #<imm>] Thumb Store Store Register Byte (Wide)
0x04600000 strbt STRBT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Store Register Byte Unprivileged
0x016000F0 strd STRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] Thumb Store Store Register Dual (Thumb)
0xE8400000 strex STREX <Rd>, <Rt>, [<Rn>] Thumb Store Excl Store Register Exclusive (Thumb)
0x01C00F90 strexb STREXB<c> <Rd>, <Rt>, [<Rn>] Load/Store Excl Store Register Exclusive Byte (A32)
0xE8C00F40 strexb STREXB <Rd>, <Rt>, [<Rn>] Thumb Store Excl Store Register Exclusive Byte (Thumb)