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ARM Opcode Map

Reverse lookup instructions by their hexadecimal encoding.

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Opcode Mnemonic Syntax Format Name
0x0E100E10 mrc MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Register from Coprocessor (A32)
0xFE100010 mrc2 MRC2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Register from Coprocessor 2 (A32)
0x0C500E00 mrrc MRRC<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Two Registers from Coprocessor (A32)
0xFC500000 mrrc2 MRRC2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Two Registers from Coprocessor 2 (A32)
0xD5700000 mrrs MRRS <Xt>, <Xt+1>, <sysreg> System Move to Two Registers from System Register (128-bit)
0xD5300000 mrs MRS <Xt>, <system_reg> System Move System Register
0x01000200 mrs MRS <Rd>, <banked_reg> System Move from Special Register (Banked)
0xF3EF8000 mrs MRS <Rd>, <spec_reg> Thumb System Move Special Register to Register (Thumb)
0x010F0000 mrs MRS<c> <Rd>, <spec_reg> System Move Status Register to Register
0xD5100000 msr MSR <system_reg>, <Xt> System Move to System Register
0x0120F200 msr MSR <banked_reg>, <Rn> System Move to Special Register (Banked)
0x0320F000 msr MSR <spec_reg>, #<imm> System Move Immediate to Special Register (A32)
0xF3808000 msr MSR <spec_reg>, #<imm> Thumb System Move Immediate to Special Register (Thumb)
0x0120F000 msr MSR <spec_reg>, <Rn> Thumb System Move Register to Special Register (Thumb)
0x0120F000 msr MSR<c> <spec_reg>_<fields>, <Rn> System Move Register to Status Register
0xD5500000 msrr MSRR <sysreg>, <Xt>, <Xt+1> System Move Two Registers to System Register (128-bit)
0x1B008000 msub MSUB <Wd>, <Wn>, <Wm>, <Wa> Data Processing Multiply-Subtract
0x0E209C00 mul MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Multiply (Integer)
0x04100000 mul MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Integer Multiply (Predicated)
0x00000090 mul MUL{S}<c> <Rd>, <Rn>, <Rm> Multiply Multiply (A32)
0x2E205800 mvn MVN <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Bitwise NOT
0x03E00000 mvn MVN{S}<c> <Rd>, <Operand2> Data Proc Move NOT (A32)
0xEA6F0000 mvn.w MVN.W <Rd>, <Operand2> Thumb2 Data Proc Move NOT (Wide)
0x2F000400 mvni MVNI <Vd>.<T>, #<imm8> {, lsl #<shift>} SIMD Modified Imm Move NOT Immediate (Vector)
0x0417A000 neg NEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Integer Unary SVE Negate
0x2E20B800 neg NEG <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Negate
0xD503201F nop NOP System Alias No Operation
0xBF00 nop NOP Thumb System No Operation (Thumb)
0x0320F000 nop NOP<c> System No Operation (A32)
0x041EA000 not NOT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Integer Unary SVE Bitwise NOT
0x2E205800 not NOT <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Bitwise NOT
0x2A200000 orn ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise OR NOT
0x0EE01C00 orn ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Bitwise OR NOT
0xEA600000 orn.w ORN.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Bitwise OR NOT (Wide)
0x32000000 orr ORR <Wd|Wsp>, <Wn>, #<imm> Logical (Immediate) Bitwise OR (Immediate)
0x2A000000 orr ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise OR (Shifted Register)
0x0EA01C00 orr ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Bitwise OR
0x04180000 orr ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Logic SVE Bitwise OR (Predicated)
0x03800000 orr ORR{S}<c> <Rd>, <Rn>, <Operand2> Data Proc Logical OR (A32)
0xEA400000 orr.w ORR.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Bitwise OR (Wide)
0x04182000 orv ORV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Bitwise OR Reduction
0xDAC10800 pacda PACDA <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Data A)
0xDAC10800 pacda PACDA <Xd>, <Xn> Data Processing Pointer Authentication Code for Data Address (Key A)
0xDAC10C00 pacdb PACDB <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Data B)
0xDAC10C00 pacdb PACDB <Xd>, <Xn> Data Processing Pointer Authentication Code for Data Address (Key B)
0x9AC03000 pacga PACGA <Xd>, <Xn>, <Xm> Data Processing Pointer Authentication Code Generic Address
0xDAC10000 pacia PACIA <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Inst A)
0xDAC10000 pacia PACIA <Xd>, <Xn> Data Processing Pointer Authentication Code for Instruction Address (Key A)
0xDAC10400 pacib PACIB <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Inst B)
0xDAC10400 pacib PACIB <Xd>, <Xn> Data Processing Pointer Authentication Code for Instruction Address (Key B)
0x2518E400 pfalse PFALSE <Pd>.B SVE Predicate SVE Initialize Predicate to False
0x2558C000 pfirst PFIRST <Pd>.B, <Pg>, <Pn>.B SVE Predicate SVE Predicate First Active
0x06800010 pkhbt PKHBT<c> <Rd>, <Rn>, <Rm> {, LSL #<imm>} Data Proc Pack Halfword Bottom Top
0x06800050 pkhtb PKHTB<c> <Rd>, <Rn>, <Rm> {, ASR #<imm>} Data Proc Pack Halfword Top Bottom
0xF550F000 pld PLD [<Rn>, #<imm>] Load/Store Preload Data
0xF510F000 pldw PLDW [<Rn>, #<imm>] Load/Store Preload Data for Write (A32)
0xF8B0F000 pldw PLDW [<Rn>, #<imm>] Thumb Load/Store Preload Data for Write (Thumb)
0xF450F000 pli PLI [<Rn>, #<imm>] Load/Store Preload Instruction
0x2E209C00 pmul PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Polynomial Multiply
0x0E20E000 pmull PMULL <Vd>.1Q, <Vn>.1D, <Vm>.1D Crypto Polynomial Multiply Long (A64)
0x0E20E000 pmull PMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Polynomial Multiply Long
0x2519C400 pnext PNEXT <Pdn>.<T>, <Pg>, <Pdn>.<T> SVE Predicate SVE Find Next Active Predicate
0xBC00 pop POP <registers> Thumb Load Multiple Pop (Thumb)
0x08BD0000 pop POP<c> <registers> Load Multiple Pop Multiple Registers (A32)
0xE8BD0000 pop.w POP.W <registers> Thumb Load Multiple Pop (Wide)
0xF9800000 prfm PRFM <prfop>, [<Xn|SP>, #<pimm>] Load/Store Imm Prefetch Memory (Immediate)
0xD8000000 prfm PRFM <prfop>, <label> Load Literal Prefetch Memory (Literal)
0xF8A04800 prfm PRFM <prfop>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Prefetch Memory (Register)
0xD503223F psb PSB CSYNC System Alias Profiling Synchronization Barrier
0xF57FF044 pssbb PSSBB System Hint Physical Speculative Store Bypass Barrier (A32)
0xD503349F pssbb PSSBB System Hint Physical Speculation Barrier
0x2550C000 ptest PTEST <Pg>, <Pn>.B SVE Predicate SVE Predicate Test
0x2518E000 ptrue PTRUE <Pd>.<T> {, <pattern>} SVE Predicate SVE Initialize Predicate to True
0xB400 push PUSH <registers> Thumb Store Multiple Push (Thumb)
0x092D0000 push PUSH<c> <registers> Store Multiple Push Multiple Registers (A32)
0xE92D0000 push.w PUSH.W <registers> Thumb Store Multiple Push (Wide)
0x01000050 qadd QADD<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Add (A32)
0x06200F10 qadd16 QADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Add 16
0x06200F90 qadd8 QADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Add 8
0x01400050 qdadd QDADD<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Double and Add
0x01600050 qdsub QDSUB<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Double and Subtract
0x01200050 qsub QSUB<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Subtract (A32)
0x06200F70 qsub16 QSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Subtract 16
0x06200FF0 qsub8 QSUB8<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Subtract 8
0x05278000 rbit RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> SVE Permute SVE Reverse Bits
0x5AC00000 rbit RBIT <Wd>, <Wn> Data Processing Reverse Bits
0xFA90F0A0 rbit RBIT <Rd>, <Rm> Thumb Misc Reverse Bits (Thumb)
0xDAC00000 rbit RBIT <Xd>, <Xn> Data Processing Reverse Bits (64-bit)
0x06FF0F30 rbit RBIT<c> <Rd>, <Rm> Data Proc Reverse Bits (A32)
0x5920A000 rcwsswpp RCWS <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write (Soft)
0x1920A000 rcwswpp RCWSWPP <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write Swap Pair
0x19A0A000 rcwswppa RCWSWPPA <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write Swap Pair (Acquire)
0x19E0A000 rcwswppal RCWSWPPAL <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write Swap Pair (Acquire-Release)
0xD65F0000 ret RET {<Xn>} Branch Return from Subroutine
0x05383800 rev REV <Zd>.<T>, <Zn>.<T> SVE Permute SVE Reverse Vector
0xBA00 rev REV <Rd>, <Rm> Thumb Data Proc Reverse Bytes (Thumb)
0xDAC00C00 rev REV <Xd>, <Xn> Data Processing Reverse Bytes (64-bit)
0xFA90F080 rev REV <Rd>, <Rm> Thumb Misc Reverse Bytes (Thumb)
0x5AC00800 rev REV <Wd>, <Wn> Data Processing Reverse Bytes (32-bit)
0x06BF0F30 rev REV<c> <Rd>, <Rm> Data Proc Reverse Bytes (A32)