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ARM Opcode Map

Reverse lookup instructions by their hexadecimal encoding.

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Opcode Mnemonic Syntax Format Name
0x0D305E00 ldc LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Load Coprocessor (A32)
0xFD100000 ldc2 LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Load Coprocessor 2 (A32)
0xB8201000 ldclr LDCLR <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Clear Word
0xB8202000 ldeor LDEOR <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Exclusive OR Word
0xA4006000 ldff1b LDFF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Bytes
0xC5C0E000 ldff1d LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Doublewords
0xA4A06000 ldff1h LDFF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Halfwords
0x85006000 ldff1w LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Words
0xD9600000 ldg LDG <Xt>, [<Xn|SP>, #<simm>] Load/Store Load Allocation Tag
0xC800 ldm LDM <Rn>!, <registers> Thumb Load Multiple Load Multiple (Thumb)
0x08100000 ldm LDM<mode><c> <Rn>{!}, <registers> Load Multiple Load Multiple (A32)
0xE8900000 ldm.w LDM.W <Rn>{!}, <registers> Thumb Load Multiple Load Multiple (Wide)
0xA410A000 ldnf1b LDNF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Bytes
0xA5F0A000 ldnf1d LDNF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Doublewords
0xA4B0A000 ldnf1h LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Halfwords
0xA550A000 ldnf1w LDNF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Words
0x28400000 ldnp LDNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Load Pair of Registers (Non-temporal)
0x2D400000 ldp LDP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] Load/Store Pair Load Pair SIMD&FP Registers
0x29400000 ldp LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> Load/Store Pair Load Pair of Registers
0xA9400000 ldp LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> Load/Store Pair Load Pair of Registers (64-bit)
0x69400000 ldpsw LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] Load/Store Pair Load Pair of Registers Signed Word
0xBD400000 ldr LDR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] Load/Store Load SIMD&FP Register (Immediate)
0xB9400000 ldr LDR <Wt>, [<Xn|SP>, #<pimm>] Load/Store Imm Load Register (Immediate)
0x18000000 ldr LDR <Wt>, <label> Load Literal Load Register (Literal)
0xB8600800 ldr LDR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Load Register (Register)
0x041F0000 ldr LDR<c> <Rt>, <label> Load Literal Load Register PC-Relative (A32)
0x4800 ldr LDR <Rt>, <label> Thumb Load Load Register PC-Relative (Thumb)
0x05300000 ldr LDR<c> <Rt>, [<Rn>, #+/-<imm>]{!} Load/Store Load Register (A32 Immediate)
0xF8D00000 ldr.w LDR.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register (Wide)
0xF8200400 ldraa LDRAA <Xt>, [<Xn|SP>, #<simm>] Load/Store Load Register Authenticate (Key A)
0xF8A00400 ldrab LDRAB <Xt>, [<Xn|SP>, #<simm>] Load/Store Load Register Authenticate (Key B)
0x39400000 ldrb LDRB <Wt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Byte (Immediate)
0x38600800 ldrb LDRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Load Register Byte (Register)
0x05700000 ldrb LDRB<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Byte (A32)
0xF8900000 ldrb.w LDRB.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Byte (Wide)
0x04700000 ldrbt LDRBT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Byte Unprivileged
0x016000D0 ldrd LDRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] Thumb Load Load Register Dual (Thumb)
0x004000D0 ldrd LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>] Load/Store Load Register Dual (A32)
0xE8500F00 ldrex LDREX <Rt>, [<Rn>] Thumb Load Excl Load Register Exclusive (Thumb)
0x01900F9F ldrex LDREX<c> <Rt>, [<Rn>] Load/Store Load Register Exclusive (A32)
0x01D00F9F ldrexb LDREXB<c> <Rt>, [<Rn>] Load/Store Excl Load Register Exclusive Byte (A32)
0xE8D00F4F ldrexb LDREXB <Rt>, [<Rn>] Thumb Load Excl Load Register Exclusive Byte (Thumb)
0x01B00F9F ldrexd LDREXD<c> <Rt>, <Rt2>, [<Rn>] Load/Store Excl Load Register Exclusive Double (A32)
0x01F00F9F ldrexh LDREXH<c> <Rt>, [<Rn>] Load/Store Excl Load Register Exclusive Halfword (A32)
0xE8D00F5F ldrexh LDREXH <Rt>, [<Rn>] Thumb Load Excl Load Register Exclusive Halfword (Thumb)
0x79400000 ldrh LDRH <Wt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Halfword (Immediate)
0x78600800 ldrh LDRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Load Register Halfword (Register)
0x017000B0 ldrh LDRH<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Halfword (A32)
0xF8B00000 ldrh.w LDRH.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Halfword (Wide)
0x007000B0 ldrht LDRHT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Halfword Unprivileged
0x39C00000 ldrsb LDRSB <Wt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Signed Byte (Immediate)
0x39800000 ldrsb LDRSB <Xt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Signed Byte (64-bit Immediate)
0x017000D0 ldrsb LDRSB<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Byte (A32)
0xF9900000 ldrsb.w LDRSB.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Signed Byte (Wide)
0x007000D0 ldrsbt LDRSBT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Byte Unprivileged
0x017000F0 ldrsh LDRSH<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Halfword (A32)
0xF9B00000 ldrsh.w LDRSH.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Signed Halfword (Wide)
0x007000F0 ldrsht LDRSHT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Halfword Unprivileged
0xB9800000 ldrsw LDRSW <Xt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Signed Word (Immediate)
0x98000000 ldrsw LDRSW <Xt>, <label> Load Literal Load Register Signed Word (Literal)
0x04300000 ldrt LDRT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Unprivileged
0xB8203000 ldset LDSET <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Set Word
0xB8204000 ldsmax LDSMAX <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Signed Maximum Word
0xB8205000 ldsmin LDSMIN <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Signed Minimum Word
0xB8400800 ldtr LDTR <Wt>, [<Xn|SP>, #<simm>] Load/Store Load Register (Unprivileged)
0xB8206000 ldumax LDUMAX <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Unsigned Maximum Word
0xB8207000 ldumin LDUMIN <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Unsigned Minimum Word
0xB8400000 ldur LDUR <Wt>, [<Xn|SP>, #<simm>] Load/Store Load Register (Unscaled)
0x887F0000 ldxp LDXP <Wt1>, <Wt2>, [<Xn|SP>] Load/Store Excl Load Exclusive Pair
0x885F7C00 ldxr LDXR <Wt>, [<Xn|SP>] Load/Store Excl Load Exclusive Register
0x1AC02000 lsl LSLV <Wd>, <Wn>, <Wm> Data Processing Logical Shift Left (Register)
0x04138000 lsl LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Shift SVE Shift Left (Predicated)
0x01A00010 lsl LSL{S}<c> <Rd>, <Rm>, <Rs> Data Proc Logical Shift Left (A32)
0x1AC02400 lsr LSRV <Wd>, <Wn>, <Wm> Data Processing Logical Shift Right (Register)
0x04118000 lsr LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Shift SVE Logical Shift Right (Predicated)
0x01A00030 lsr LSR{S}<c> <Rd>, <Rm>, <Rs> Data Proc Logical Shift Right (A32)
0x1B000000 madd MADD <Wd>, <Wn>, <Wm>, <Wa> Data Processing Multiply-Add
0x9B000000 madd MADD <Xd>, <Xn>, <Xm>, <Xa> Data Processing Multiply-Add (64-bit)
0x0E000E10 mcr MCR<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Coprocessor from Register (A32)
0xFE000010 mcr2 MCR2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Coprocessor from Register 2 (A32)
0x0C400E00 mcrr MCRR<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Coprocessor from Two Registers (A32)
0xFC400000 mcrr2 MCRR2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Coprocessor from Two Registers 2 (A32)
0x0E200010 mia MIA<c> <Acc>, <Rn>, <Rm> Coprocessor Multiply with Internal Accumulate
0x0E280010 miaph MIAPH<c> <Acc>, <Rn>, <Rm> Coprocessor Multiply with Internal Accumulate Packed Halfwords
0x0E209400 mla MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Multiply-Accumulate
0xFB000000 mla MLA <Rd>, <Rm>, <Ra>, <Rn> Thumb Mul Multiply Accumulate (Thumb)
0x00200090 mla MLA{S}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Multiply Accumulate (A32)
0x2E209400 mls MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Multiply-Subtract
0xFB000010 mls MLS <Rd>, <Rm>, <Ra>, <Rn> Thumb Mul Multiply Subtract (Thumb)
0x00600090 mls MLS<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Multiply Subtract (A32)
0x0EA01C00 mov MOV <Vd>.<T>, <Vn>.<T> SIMD Alias Vector Move (Register)
0x6E000400 mov MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] SIMD Copy Move Element to Element
0x03A00000 mov MOV{S}<c> <Rd>, <Operand2> Data Proc Move (A32)
0xEA4F0000 mov.w MOV.W <Rd>, <Operand2> Thumb2 Data Proc Move (Wide)
0x0F000400 movi MOVI <Vd>.<T>, #<imm8> {, lsl #<shift>} SIMD Modified Imm Move Immediate (Vector)
0x72800000 movk MOVK <Wd>, #<imm16> {, lsl #<shift>} Data Processing Move Keep
0x12800000 movn MOVN <Wd>, #<imm16> {, lsl #<shift>} Data Processing Move Not
0x03400000 movt MOVT<c> <Rd>, #<imm16> Data Proc Move Top (A32)
0x03000000 movw MOVW<c> <Rd>, #<imm16> Data Proc Move Word (A32)
0x52800000 movz MOVZ <Wd>, #<imm16> {, lsl #<shift>} Data Processing Move Zero