ARM Opcode Map
Reverse lookup instructions by their hexadecimal encoding.
| Opcode | Mnemonic | Syntax | Format | Name |
|---|---|---|---|---|
| 0xD50330BF | dmb | DMB <option> | System | Data Memory Barrier |
| 0xF3BF8F50 | dmb | DMB <option> | Thumb System | Data Memory Barrier (Thumb) |
| 0xF57FF050 | dmb | DMB <option> | System | Data Memory Barrier (A32) |
| 0xD6BF03E0 | drps | DRPS | System | Debug Restore PE State |
| 0xD503309F | dsb | DSB <option> | System | Data Synchronization Barrier |
| 0xF3BF8F40 | dsb | DSB <option> | Thumb System | Data Synchronization Barrier (Thumb) |
| 0xF57FF040 | dsb | DSB <option> | System | Data Synchronization Barrier (A32) |
| 0x0E000C00 | dup | DUP <Vd>.<T>, <R><n> | SIMD Copy | Duplicate Vector Element (Scalar) |
| 0x0E000400 | dup | DUP <Vd>.<T>, <Vn>.<Ts>[<index>] | SIMD Copy | Duplicate Vector Element (Element) |
| 0x05203800 | dup | DUP <Zd>.<T>, <R><n|m> | SVE Move | SVE Duplicate Scalar |
| 0x4A200000 | eon | EON <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise Exclusive OR NOT |
| 0xCA200000 | eon | EON <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Bitwise Exclusive OR NOT (64-bit) |
| 0x52000000 | eor | EOR <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Bitwise Exclusive OR (Immediate) |
| 0x4A000000 | eor | EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise Exclusive OR (Register) |
| 0x2E201C00 | eor | EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Bitwise Exclusive OR |
| 0x04190000 | eor | EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE Bitwise Exclusive OR (Predicated) |
| 0x00200000 | eor | EOR{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | Exclusive OR (A32) |
| 0xEA800000 | eor.w | EOR.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | Bitwise Exclusive OR (Wide) |
| 0x04192000 | eorv | EORV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE Bitwise EOR Reduction |
| 0xD69F03E0 | eret | ERET | System | Exception Return |
| 0x0160006E | eret | ERET | System | Exception Return (A32) |
| 0xF3DE8F00 | eret | ERET | Thumb System | Exception Return (Thumb) |
| 0x0320F010 | esb | ESB | System Hint | Error Synchronization Barrier (A32) |
| 0xD503221F | esb | ESB | System Alias | Error Synchronization Barrier |
| 0x05200000 | ext | EXT <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm> | SVE Permute | SVE Extract Vector |
| 0x2E000000 | ext | EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index> | SIMD Extract | Extract Vector |
| 0x13800000 | extr | EXTR <Wd>, <Wn>, <Wm>, #<lsb> | Data Processing | Extract |
| 0x93C00000 | extr | EXTR <Xd>, <Xn>, <Xm>, #<lsb> | Data Processing | Extract (64-bit) |
| 0x041CA000 | fabs | FABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE Floating-Point Absolute Value |
| 0x1E20C000 | fabs | FABS <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Absolute Value (Scalar) |
| 0x0EA0F800 | fabs | FABS <Vd>.<T>, <Vn>.<T> | SIMD Two Register | Vector Floating-Point Absolute Value |
| 0x0EF8F800 | fabs | FABS <Vd>.8H, <Vn>.8H | NEON FP16 | Floating-Point Absolute Value (Half-Precision) |
| 0x1E202800 | fadd | FADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Add (Scalar) |
| 0x0E20D400 | fadd | FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Add |
| 0x65000000 | fadd | FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE Floating-Point Add |
| 0x0E401400 | fadd | FADD <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Add (Half-Precision) |
| 0x1E202800 | fadd | FADD <Sd>, <Sn>, <Sm> | Float Data Proc | Floating-point Add (Single) |
| 0x1E602800 | fadd | FADD <Dd>, <Dn>, <Dm> | Float Data Proc | Floating-point Add (Double) |
| 0x2E20D400 | faddp | FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Add Pairwise |
| 0x65002000 | faddv | FADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE Floating-Point Add Reduction |
| 0x64008000 | fcadd | FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, #<rot> | SVE FP Complex | SVE Floating-Point Complex Add |
| 0x2E00E400 | fcadd | FCADD <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> | NEON Complex | Floating-Point Complex Add (NEON) |
| 0x1E200400 | fccmp | FCCMP <Hn|Sn|Dn>, <Hm|Sm|Dm>, #<nzcv>, <cond> | FP Compare | Floating-Point Conditional Compare (Scalar) |
| 0x65006000 | fcmeq | FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE FP Compare | SVE Floating-Point Compare Equal |
| 0x65004010 | fcmgt | FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE FP Compare | SVE Floating-Point Compare Greater Than |
| 0x64000000 | fcmla | FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, #<rot> | SVE FP Complex | SVE Floating-Point Complex Multiply-Add |
| 0x2E00C400 | fcmla | FCMLA <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> | NEON Complex | Floating-Point Complex Multiply Accumulate (NEON) |
| 0x1E202000 | fcmp | FCMP <Hn|Sn|Dn>, <Hm|Sm|Dm|#0.0> | FP Compare | Floating-Point Compare (Scalar) |
| 0x1E202000 | fcmp | FCMP <Sn>, <Sm> | Float Compare | Floating-point Compare (Single) |
| 0x1E602000 | fcmp | FCMP <Dn>, <Dm> | Float Compare | Floating-point Compare (Double) |
| 0x1E200C00 | fcsel | FCSEL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <cond> | FP Data Processing | Floating-Point Conditional Select (Scalar) |
| 0x1EE24000 | fcvt | FCVT <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert (Scalar) |
| 0x1EE40000 | fcvtas | FCVTAS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Signed Integer (Nearest) |
| 0x1EE50000 | fcvtau | FCVTAU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Unsigned Integer (Nearest) |
| 0x0E217800 | fcvtl | FCVTL <Vd>.4S, <Vn>.4H | NEON FP16 | Floating-Point Convert Long (Half to Single) |
| 0x0E217800 | fcvtl | FCVTL <Vd>.<Td>, <Vn>.<Ts> | SIMD Two Register | Vector Floating-Point Convert Long |
| 0x0E217800 | fcvtl2 | FCVTL2 <Vd>.4S, <Vn>.8H | NEON FP16 | Floating-Point Convert Long High (Half to Single) |
| 0x1E300000 | fcvtms | FCVTMS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Signed Integer (Minus Infinity) |
| 0x1E310000 | fcvtmu | FCVTMU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Unsigned Integer (Minus Infinity) |
| 0x0E216800 | fcvtn | FCVTN <Vd>.4H, <Vn>.4S | NEON FP16 | Floating-Point Convert Narrow (Single to Half) |
| 0x0E216800 | fcvtn | FCVTN <Vd>.<Td>, <Vn>.<Ts> | SIMD Two Register | Vector Floating-Point Convert Narrow |
| 0x0E216800 | fcvtn2 | FCVTN2 <Vd>.8H, <Vn>.4S | NEON FP16 | Floating-Point Convert Narrow High (Single to Half) |
| 0x1E200000 | fcvtns | FCVTNS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Signed Integer (Nearest, ties to Even) |
| 0x1E210000 | fcvtnu | FCVTNU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Unsigned Integer (Nearest, ties to Even) |
| 0x1E280000 | fcvtps | FCVTPS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Signed Integer (Plus Infinity) |
| 0x1E290000 | fcvtpu | FCVTPU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating-Point Convert to Unsigned Integer (Plus Infinity) |
| 0x655AA000 | fcvtzs | FCVTZS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE Floating-Point Convert to Signed Integer |
| 0x1E380000 | fcvtzs | FCVTZS <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} | FP Conversion | Floating-Point Convert to Signed Integer (Zero) |
| 0x9E380000 | fcvtzs | FCVTZS <Xd>, <Dn> | Float Conversion | Floating-point Convert to Signed Integer (Round towards Zero) |
| 0x0F00FC00 | fcvtzs | FCVTZS <Vd>.<T>, <Vn>.<T> {, #<fbits>} | SIMD Two Register | Vector Floating-Point Convert to Signed Integer |
| 0x655BA000 | fcvtzu | FCVTZU <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE Floating-Point Convert to Unsigned Integer |
| 0x1E390000 | fcvtzu | FCVTZU <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} | FP Conversion | Floating-Point Convert to Unsigned Integer (Zero) |
| 0x2F00FC00 | fcvtzu | FCVTZU <Vd>.<T>, <Vn>.<T> {, #<fbits>} | SIMD Two Register | Vector Floating-Point Convert to Unsigned Integer |
| 0x1E201800 | fdiv | FDIV <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Divide (Scalar) |
| 0x2E20FC00 | fdiv | FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Divide |
| 0x650D8000 | fdiv | FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE Floating-Point Divide |
| 0x2E403C00 | fdiv | FDIV <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Divide (Half-Precision) |
| 0x1E201800 | fdiv | FDIV <Sd>, <Sn>, <Sm> | Float Data Proc | Floating-point Divide (Single) |
| 0x1E601800 | fdiv | FDIV <Dd>, <Dn>, <Dm> | Float Data Proc | Floating-point Divide (Double) |
| 0x1E7E0000 | fjcvtzs | FJCVTZS <Wd>, <Dn> | Float Convert | Floating-Point Javascript Convert |
| 0x1F000000 | fmadd | FMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating-Point Fused Multiply-Add (Scalar) |
| 0x1E204800 | fmax | FMAX <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Maximum (Scalar) |
| 0x0E20F400 | fmax | FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Maximum |
| 0x65068000 | fmax | FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE Floating-Point Maximum |
| 0x0E403400 | fmax | FMAX <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Maximum (Half-Precision) |
| 0x1E206800 | fmaxnm | FMAXNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Max Number (Scalar) |
| 0x2E20F400 | fmaxp | FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Max Pairwise |
| 0x65062000 | fmaxv | FMAXV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE Floating-Point Maximum Reduction |
| 0x0E30F800 | fmaxv | FMAXV <Sd>, <Vn>.<T> | NEON Reduction | Floating-Point Maximum Reduction (NEON) |
| 0x1E205800 | fmin | FMIN <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Minimum (Scalar) |
| 0x0EA0F400 | fmin | FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Minimum |
| 0x65078000 | fmin | FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE Floating-Point Minimum |
| 0x0EC03400 | fmin | FMIN <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Minimum (Half-Precision) |
| 0x1E207800 | fminnm | FMINNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Min Number (Scalar) |
| 0x2EA0F400 | fminp | FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Min Pairwise |
| 0x65072000 | fminv | FMINV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE Floating-Point Minimum Reduction |
| 0x0EB0F800 | fminv | FMINV <Sd>, <Vn>.<T> | NEON Reduction | Floating-Point Minimum Reduction (NEON) |
| 0x0E20CC00 | fmla | FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Multiply-Accumulate |
| 0x65200000 | fmla | FMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> | SVE FP Ternary | SVE Floating-Point Fused Multiply-Add |
| 0x0E400C00 | fmla | FMLA <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Multiply Accumulate (Half-Precision) |