ARM Opcode Map
Reverse lookup instructions by their hexadecimal encoding.
| Opcode | Mnemonic | Syntax | Format | Name |
|---|---|---|---|---|
| 0x0EA0CC00 | fmls | FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Multiply-Subtract |
| 0x65202000 | fmls | FMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> | SVE FP Ternary | SVE Floating-Point Fused Multiply-Subtract |
| 0x0EC00C00 | fmls | FMLS <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Multiply Subtract (Half-Precision) |
| 0x1E201000 | fmov | FMOV <Hd|Sd|Dd>, #<fimm> | FP Immediate | Floating-Point Move (Immediate) |
| 0x1E204000 | fmov | FMOV <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Move (Register) |
| 0x1E260000 | fmov | FMOV <Wd|Xd>, <Sn|Dn> | FP Conversion | Floating-Point Move (General) |
| 0x1E270000 | fmov | FMOV <Sd|Dd>, <Wn|Xn> | FP Conversion | Floating-Point Move (General to FP) |
| 0x1E604000 | fmov | FMOV <Dd>, <Dn> | Float Data Proc | Floating-point Move (Register) |
| 0x1E601000 | fmov | FMOV <Dd>, #<imm> | Float Imm | Floating-point Move (Immediate) |
| 0x1F008000 | fmsub | FMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating-Point Fused Multiply-Subtract (Scalar) |
| 0x1E200800 | fmul | FMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Multiply (Scalar) |
| 0x2E20DC00 | fmul | FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Multiply |
| 0x65028000 | fmul | FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE Floating-Point Multiply |
| 0x2E401C00 | fmul | FMUL <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Multiply (Half-Precision) |
| 0x1E200800 | fmul | FMUL <Sd>, <Sn>, <Sm> | Float Data Proc | Floating-point Multiply (Single) |
| 0x1E600800 | fmul | FMUL <Dd>, <Dn>, <Dm> | Float Data Proc | Floating-point Multiply (Double) |
| 0x041DA000 | fneg | FNEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE Floating-Point Negate |
| 0x1EE14000 | fneg | FNEG <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Negate (Scalar) |
| 0x2EA0F800 | fneg | FNEG <Vd>.<T>, <Vn>.<T> | SIMD Two Register | Vector Floating-Point Negate |
| 0x2EF8F800 | fneg | FNEG <Vd>.8H, <Vn>.8H | NEON FP16 | Floating-Point Negate (Half-Precision) |
| 0x1F200000 | fnmadd | FNMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating-Point Fused Negated Multiply-Add (Scalar) |
| 0x1F208000 | fnmsub | FNMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating-Point Fused Negated Multiply-Subtract (Scalar) |
| 0x1E208800 | fnmul | FNMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Negated Multiply (Scalar) |
| 0x0EF9D800 | frecpe | FRECPE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | Vector Floating-Point Reciprocal Estimate |
| 0x0E20FC00 | frecps | FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Reciprocal Step |
| 0x1E28C000 | frint32x | FRINT32X <Sd>, <Sn> | Float Conversion | Floating-Point Round to 32-bit Integer (Exact) |
| 0x1E284000 | frint32z | FRINT32Z <Sd>, <Sn> | Float Conversion | Floating-Point Round to 32-bit Integer (Zero) |
| 0x1E29C000 | frint64x | FRINT64X <Sd>, <Sn> | Float Conversion | Floating-Point Round to 64-bit Integer (Exact) |
| 0x1E294000 | frint64z | FRINT64Z <Sd>, <Sn> | Float Conversion | Floating-Point Round to 64-bit Integer (Zero) |
| 0x1E264000 | frinta | FRINTA <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Round to Integral (Nearest) |
| 0x1E27C000 | frinti | FRINTI <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Round to Integral (Current) |
| 0x1E254000 | frintm | FRINTM <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Round to Integral (Minus Infinity) |
| 0x1E244000 | frintn | FRINTN <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Round to Integral (Nearest Even) |
| 0x1E24C000 | frintp | FRINTP <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Round to Integral (Plus Infinity) |
| 0x1E274000 | frintx | FRINTX <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Round to Integral (Exact) |
| 0x1E25C000 | frintz | FRINTZ <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Round to Integral (Zero) |
| 0x2EF9D800 | frsqrte | FRSQRTE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | Vector Floating-Point Reciprocal Sqrt Estimate |
| 0x0EA0FC00 | frsqrts | FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Reciprocal Sqrt Step |
| 0x650DA000 | fsqrt | FSQRT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE Floating-Point Square Root |
| 0x1E21C000 | fsqrt | FSQRT <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating-Point Square Root (Scalar) |
| 0x2EA1F800 | fsqrt | FSQRT <Vd>.<T>, <Vn>.<T> | SIMD Two Register | Vector Floating-Point Square Root |
| 0x2EF9F800 | fsqrt | FSQRT <Vd>.8H, <Vn>.8H | NEON FP16 | Floating-Point Square Root (Half-Precision) |
| 0x1E203800 | fsub | FSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating-Point Subtract (Scalar) |
| 0x0EC01400 | fsub | FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Floating-Point Subtract |
| 0x65018000 | fsub | FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE Floating-Point Subtract |
| 0x0EC01400 | fsub | FSUB <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | Floating-Point Subtract (Half-Precision) |
| 0x1E203800 | fsub | FSUB <Sd>, <Sn>, <Sm> | Float Data Proc | Floating-point Subtract (Single) |
| 0x1E603800 | fsub | FSUB <Dd>, <Dn>, <Dm> | Float Data Proc | Floating-point Subtract (Double) |
| 0xD52B7720 | gcspopm | GCSPOPM | System | Guarded Control Stack Pop |
| 0xD50B7740 | gcsss1 | GCSSS1 <Xt> | System | Guarded Control Stack Switch Stack 1 |
| 0xD52B7760 | gcsss2 | GCSSS2 <Xt> | System | Guarded Control Stack Switch Stack 2 |
| 0x9AC01400 | gmi | GMI <Xd>, <Xn|SP>, <Xm> | Data Processing | Get Memory Tag Intersection |
| 0xD503201F | hint | HINT #<imm> | System | Hint |
| 0xD4400000 | hlt | HLT #<imm> | Exception | Halting Debug-mode |
| 0xBA80 | hlt | HLT #<imm> | Thumb System | Halting Debug (Thumb) |
| 0x01000070 | hlt | HLT #<imm> | System | Halting Debug (A32) |
| 0xD4000002 | hvc | HVC #<imm> | Exception | Hypervisor Call |
| 0xF7E08000 | hvc | HVC #<imm> | Thumb System | Hypervisor Call (Thumb) |
| 0x01400070 | hvc | HVC #<imm> | System | Hypervisor Call (A32) |
| 0xD5087000 | ic | IC <op> {, <Xt>} | System Alias | Instruction Cache Operation |
| 0x0430E000 | incb | INCB <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE Increment Scalar by Byte Count |
| 0x04F0E000 | incd | INCD <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE Increment Scalar by Doubleword Count |
| 0x04B0E000 | incw | INCW <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE Increment Scalar by Word Count |
| 0x04204C00 | index | INDEX <Zd>.<T>, <Start>, <Step> | SVE Index | SVE Create Index Vector |
| 0x4E001C00 | ins | INS <Vd>.<Ts>[<index>], <Rn> | SIMD Copy | Insert Vector Element (General) |
| 0x05243800 | insr | INSR <Zdn>.<T>, <R><m> | SVE Move | SVE Insert Scalar |
| 0x9AC01000 | irg | IRG <Xd|SP>, <Xn|SP>{, <Xm>} | Data Processing | Insert Random Tag |
| 0xD50330DF | isb | ISB {<option>} | System | Instruction Synchronization Barrier |
| 0xF3BF8F60 | isb | ISB <option> | Thumb System | Instruction Synchronization Barrier (Thumb) |
| 0xF57FF060 | isb | ISB <option> | System | Instruction Synchronization Barrier (A32) |
| 0xBF00 | it | IT{x{y{z}}} <cond> | Thumb IT | If-Then (Thumb) |
| 0x05228000 | lasta | LASTA <Vd>.<T>, <Pg>, <Zn>.<T> | SVE Extract | SVE Extract Last Element After |
| 0x05238000 | lastb | LASTB <Vd>.<T>, <Pg>, <Zn>.<T> | SVE Extract | SVE Extract Last Element Before |
| 0x0D400000 | ld1 | LD1 { <Vt>.<T>, ... }, [<Xn|SP>] | SIMD Load/Store | Load Multiple Single Elements |
| 0xA4004000 | ld1b | LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE Load Contiguous Bytes |
| 0xC5C0C000 | ld1d | LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE Load Contiguous Doublewords |
| 0xA4A0A000 | ld1h | LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE Load Contiguous Halfwords |
| 0x0D40C000 | ld1r | LD1R { <Vt>.<T> }, [<Xn|SP>] | SIMD Load/Store | Load Single Element Replicate |
| 0xA540A000 | ld1w | LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE Load Contiguous Words |
| 0x85204000 | ld1w | LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, SXTW #<shift>] | SVE Gather | SVE Gather Load Words (Vector Index) |
| 0x0C408000 | ld2 | LD2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | Load Multiple 2-Element Structures |
| 0x0D60C000 | ld2r | LD2R { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | Load 2-Element Structure Replicate |
| 0x0C404000 | ld3 | LD3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] | SIMD Load/Store | Load Multiple 3-Element Structures |
| 0x0C400000 | ld4 | LD4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] | SIMD Load/Store | Load Multiple 4-Element Structures |
| 0xF83FD000 | ld64b | LD64B <Xt>, [<Xn|SP>] | Load/Store | Single-copy Atomic 64-byte Load |
| 0x01900C9F | lda | LDA<c> <Rt>, [<Rn>] | Load/Store | Load Acquire (A32) |
| 0xB8200000 | ldadd | LDADD <Ws>, <Wt>, [<Xn|SP>] | Atomic | Atomic Load-Add Word |
| 0x01900E9F | ldaex | LDAEX<c> <Rt>, [<Rn>] | Load/Store | Load Acquire Exclusive (A32) |
| 0x01D00E9F | ldaexb | LDAEXB<c> <Rt>, [<Rn>] | Load Excl | Load Acquire Exclusive Byte (A32) |
| 0x01B00E9F | ldaexd | LDAEXD<c> <Rt>, <Rt2>, [<Rn>] | Load Excl | Load Acquire Exclusive Double (A32) |
| 0x01F00E9F | ldaexh | LDAEXH<c> <Rt>, [<Rn>] | Load Excl | Load Acquire Exclusive Halfword (A32) |
| 0xB8BFC000 | ldapr | LDAPR <Wt>, [<Xn|SP>] | Load/Store | Load-Acquire RCpc Register |
| 0x38BFC000 | ldaprb | LDAPRB <Wt>, [<Xn|SP>] | Load/Store | Load-Acquire RCpc Register Byte |
| 0x78BFC000 | ldaprh | LDAPRH <Wt>, [<Xn|SP>] | Load/Store | Load-Acquire RCpc Register Halfword |
| 0x88DFFC00 | ldar | LDAR <Wt>, [<Xn|SP>] | Load/Store | Load-Acquire Register |
| 0x08DFFC00 | ldarb | LDARB <Wt>, [<Xn|SP>] | Load/Store | Load-Acquire Register Byte |
| 0x48DFFC00 | ldarh | LDARH <Wt>, [<Xn|SP>] | Load/Store | Load-Acquire Register Halfword |
| 0x885FFC00 | ldaxr | LDAXR <Wt>, [<Xn|SP>] | Load/Store Excl | Load-Acquire Exclusive Register |
| 0x085FFC00 | ldaxrb | LDAXRB <Wt>, [<Xn|SP>] | Load/Store Excl | Load-Acquire Exclusive Register Byte |
| 0x485FFC00 | ldaxrh | LDAXRH <Wt>, [<Xn|SP>] | Load/Store Excl | Load-Acquire Exclusive Register Halfword |