fmopa

Floating-Point Matrix Outer Product Accumulate

FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S

Computes (Zn x Zm) + ZA (Outer Product) for floats.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
10
31:30
000000100
29:21
Zm
20:16
Pm
15:13
Pn
12:10
Zn
9:5
0
4
0
3
0
2
ZAda
1:0
 
Format SME Arithmetic
Opcode 0x80800000
Extension SME

Related

More in SME

Reference

Instruction Forms

Encoding Instruction ISA Bit pattern
0x80A00008 FMOPA <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B A64 10 | 000000101 | Zm | Pm | Pn | Zn | 0 | 1 | 00 | ZAda
0x80A00000 FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B A64 10 | 000000101 | Zm | Pm | Pn | Zn | 0 | 0 | 0 | ZAda
0x81A00000 FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H A64 10 | 000001101 | Zm | Pm | Pn | Zn | 0 | 0 | 0 | ZAda
0x81800008 FMOPA <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H A64 10 | 000001100 | Zm | Pm | Pn | Zn | 0 | 1 | 00 | ZAda
0x80800000 FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S A64 10 | 000000100 | Zm | Pm | Pn | Zn | 0 | 0 | 0 | ZAda
0x80C00000 FMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.D, <Zm>.D A64 10 | 000000110 | Zm | Pm | Pn | Zn | 0 | 0 | ZAda

Description

The half-precision variant works with a 16-bit element ZA tile. The single-precision variant works with a 32-bit element ZA tile. The double-precision variant works with a 64-bit element ZA tile. These instructions generate an outer product of the first source vector and the second source vector. In case of the half-precision variant, the first source is SVLH×1 vector and the second source is 1×SVLH vector. In case of the single-precision variant, the first source is SVLS×1 vector and the second source is 1×SVLS vector. In case of the double-precision variant, the first source is SVLD×1 vector and the second source is 1×SVLD vector. Each source vector is independently predicated by a corresponding governing predicate. When either source vector element is Inactive the corresponding destination tile element remains unmodified. The resulting outer product, SVLH×SVLH in case of half-precision variant, SVLS×SVLS in case of single-precision variant or SVLD×SVLD in case of double-precision variant, is then destructively added to the destination tile. This is equivalent to performing a single multiply-accumulate to each of the destination tile elements. This instruction follows SME ZA-targeting floating-point behaviors. ID_AA64SMFR0_EL1.F64F64 indicates whether the double-precision variant is implemented, and ID_AA64SMFR0_EL1.F16F16 indicates whether the half-precision variant is implemented.

Operation

CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer dim = VL DIV esize;
bits(PL) mask1 = P[a, PL];
bits(PL) mask2 = P[b, PL];
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(dim*dim*esize) operand3 = ZAtile[da, esize, dim*dim*esize];
bits(dim*dim*esize) result;

for row = 0 to dim-1
    for col = 0 to dim-1
        bits(esize) element1 = Elem[operand1, row, esize];
        bits(esize) element2 = Elem[operand2, col, esize];
        bits(esize) element3 = Elem[operand3, row*dim+col, esize];

        if (ActivePredicateElement(mask1, row, esize) &&
              ActivePredicateElement(mask2, col, esize)) then
            if sub_op then element1 = FPNeg(element1, FPCR);
            Elem[result, row*dim+col, esize] = FPMulAdd_ZA(element3, element1, element2, FPCR);
        else
            Elem[result, row*dim+col, esize] = element3;

ZAtile[da, esize, dim*dim*esize] = result;