umopa
Unsigned Integer Matrix Outer Product Accumulate
Computes outer product for unsigned integers.
Pseudocode Operation
No pseudocode available.
Encoding
Operands
-
ZAda
Dest Tile -
Zn
Col Vector -
Zm
Row Vector
Related
More in SME
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xA1800008 | UMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H | A64 | 10 | 10000 | 1 | 100 | Zm | Pm | Pn | Zn | 0 | 1 | 0 | ZAda | ||
| 0xA1A00000 | UMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B | A64 | 10 | 10000 | 1 | 10 | 1 | Zm | Pm | Pn | Zn | 0 | 0 | 0 | ZAda | ||
| 0xA1E00000 | UMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H | A64 | 10 | 10000 | 1 | 11 | 1 | Zm | Pm | Pn | Zn | 0 | 0 | ZAda |
Description
The 8-bit integer variant works with a 32-bit element ZA tile. The 16-bit integer variant works with a 64-bit element ZA tile. The unsigned integer sum of outer products and accumulate instructions multiply the sub-matrix in the first source vector by the sub-matrix in the second source vector. In case of the 8-bit integer variant, the first source holds SVLS×4 sub-matrix of unsigned 8-bit integer values, and the second source holds 4×SVLS sub-matrix of unsigned 8-bit integer values. In case of the 16-bit integer variant, the first source holds SVLD×4 sub-matrix of unsigned 16-bit integer values, and the second source holds 4×SVLD sub-matrix of unsigned 16-bit integer values. Each source vector is independently predicated by a corresponding governing predicate. When an 8-bit source element in case of 8-bit integer variant or a 16-bit source element in case of 16-bit integer variant is Inactive, it is treated as having the value 0. The resulting SVLS×SVLS widened 32-bit integer or SVLD×SVLD widened 64-bit integer sum of outer products is then destructively added to the 32-bit integer or 64-bit integer destination tile, respectively for 8-bit integer and 16-bit integer instruction variants. This is equivalent to performing a 4-way dot product and accumulate to each of the destination tile elements. In case of the 8-bit integer variant, each 32-bit container of the first source vector holds 4 consecutive column elements of each row of a SVLS×4 sub-matrix, and each 32-bit container of the second source vector holds 4 consecutive row elements of each column of a 4×SVLS sub-matrix. In case of the 16-bit integer variant, each 64-bit container of the first source vector holds 4 consecutive column elements of each row of a SVLD×4 sub-matrix, and each 64-bit container of the second source vector holds 4 consecutive row elements of each column of a 4×SVLD sub-matrix. ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.
Operation
CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer dim = VL DIV esize;
bits(PL) mask1 = P[a, PL];
bits(PL) mask2 = P[b, PL];
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(dim*dim*esize) operand3 = ZAtile[da, esize, dim*dim*esize];
bits(dim*dim*esize) result;
integer prod;
for row = 0 to dim-1
for col = 0 to dim-1
bits(esize) sum = Elem[operand3, row*dim+col, esize];
for k = 0 to 3
if ActivePredicateElement(mask1, 4*row + k, esize DIV 4) &&
ActivePredicateElement(mask2, 4*col + k, esize DIV 4) then
prod = (Int(Elem[operand1, 4*row + k, esize DIV 4], op1_unsigned) *
Int(Elem[operand2, 4*col + k, esize DIV 4], op2_unsigned));
if sub_op then prod = -prod;
sum = sum + prod;
Elem[result, row*dim+col, esize] = sum;
ZAtile[da, esize, dim*dim*esize] = result;