psel

Predicate Select

PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]

Selects a predicate register based on a boolean condition (SME2).

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
00100101
31:24
i1
23
tszh
22
1
21
tszl
20:18
Rv
17:16
01
15:14
Pn
13:10
0
9
Pm
8:5
0
4
Pd
3:0
 
Format SME2
Opcode 0x25204000
Extension SME2

Operands

  • Pd
    Dest
  • Pn
    True
  • Pm
    Predicate Array

Related

More in SME2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x25204000 PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>] A64 00100101 | i1 | tszh | 1 | tszl | Rv | 01 | Pn | 0 | Pm | 0 | Pd

Description

If the indexed element of the second source predicate is true, place the contents of the first source predicate register into the destination predicate register, otherwise set the destination predicate to all-false. The indexed element is determined by the sum of a general-purpose index register and an immediate, modulo the number of elements. Does not set the condition flags. For programmer convenience, an assembler must also accept predicate-as-counter register names for the destination predicate register and the first source predicate register.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) operand1 = P[n, PL];
bits(PL) operand2 = P[m, PL];
bits(32) idx = X[v, 32];
integer element = (UInt(idx) + imm) MOD elements;
bits(PL) result;

if ActivePredicateElement(operand2, element, esize) then
    result = operand1;
else
    result = Zeros(PL);

P[d, PL] = result;