smax

Multi-vector Signed Maximum (SME2)

SMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }

Signed maximum of 2 or 4 vectors.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
11000001
31:24
size
23:22
1
21
Zm
20:17
0101100
16:10
000
9:7
0
6
0
5
Zdn
4:1
0
0
 
Format SME2 Int
Opcode 0xC120B000
Extension SME2

Related

Other forms of smax

  • smax SVE Signed Maximum
  • smax Vector Signed Maximum

More in SME2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E206400 SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 0110 | 0 | 1 | Rn | Rd
0x11C00000 SMAX <Wd>, <Wn>, #<simm> A64 0 | 0 | 0 | 1000111 | 0000 | imm8 | Rn | Rd
0x91C00000 SMAX <Xd>, <Xn>, #<simm> A64 1 | 0 | 0 | 1000111 | 0000 | imm8 | Rn | Rd
0xC120A000 SMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101000 | 0000 | 0 | Zdn | 0
0xC120A800 SMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101010 | 0000 | 0 | Zdn | 0 | 0
0xC120B000 SMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } A64 11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 0 | Zdn | 0
0xC120B800 SMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } A64 11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 0 | Zdn | 0 | 0
0x1AC06000 SMAX <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 011000 | Rn | Rd
0x9AC06000 SMAX <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 011000 | Rn | Rd
0x04080000 SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 001 | 0 | 0 | 0 | 000 | Pg | Zm | Zdn
0x2528C000 SMAX <Zdn>.<T>, <Zdn>.<T>, #<imm> A64 00100101 | size | 101 | 00 | 0 | 11 | 0 | imm8 | Zdn

Description

Determine the signed maximum of elements of the two or four second source vectors and the corresponding elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors. This instruction is unpredicated.

Operation

CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
array [0..3] of bits(VL) results;

for r = 0 to nreg-1
    bits(VL) operand1 = Z[dn+r, VL];
    bits(VL) operand2 = Z[m+r, VL];
    for e = 0 to elements-1
        integer element1 = Int(Elem[operand1, e, esize], unsigned);
        integer element2 = Int(Elem[operand2, e, esize], unsigned);
        integer res = Max(element1, element2);
        Elem[results[r], e, esize] = res<esize-1:0>;

for r = 0 to nreg-1
    Z[dn+r, VL] = results[r];