umin

Multi-vector Unsigned Minimum (SME2)

UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }

Unsigned minimum of 2 or 4 vectors.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
11000001
31:24
size
23:22
1
21
Zm
20:17
0101100
16:10
000
9:7
0
6
1
5
Zdn
4:1
1
0
 
Format SME2 Int
Opcode 0xC120B021
Extension SME2

Related

Other forms of umin

  • umin SVE Unsigned Minimum
  • umin Vector Unsigned Minimum

More in SME2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E206C00 UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 0110 | 1 | 1 | Rn | Rd
0x11CC0000 UMIN <Wd>, <Wn>, #<uimm> A64 0 | 0 | 0 | 1000111 | 0011 | imm8 | Rn | Rd
0x91CC0000 UMIN <Xd>, <Xn>, #<uimm> A64 1 | 0 | 0 | 1000111 | 0011 | imm8 | Rn | Rd
0xC120A021 UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101000 | 0000 | 1 | Zdn | 1
0xC120A821 UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101010 | 0000 | 1 | Zdn | 0 | 1
0xC120B021 UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } A64 11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 1 | Zdn | 1
0xC120B821 UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } A64 11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 1 | Zdn | 0 | 1
0x1AC06C00 UMIN <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 011011 | Rn | Rd
0x9AC06C00 UMIN <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 011011 | Rn | Rd
0x040B0000 UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 001 | 0 | 1 | 1 | 000 | Pg | Zm | Zdn
0x252BC000 UMIN <Zdn>.<T>, <Zdn>.<T>, #<imm> A64 00100101 | size | 101 | 01 | 1 | 11 | 0 | imm8 | Zdn

Description

Determine the unsigned minimum of elements of the two or four second source vectors and the corresponding elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors. This instruction is unpredicated.

Operation

CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
array [0..3] of bits(VL) results;

for r = 0 to nreg-1
    bits(VL) operand1 = Z[dn+r, VL];
    bits(VL) operand2 = Z[m+r, VL];
    for e = 0 to elements-1
        integer element1 = Int(Elem[operand1, e, esize], unsigned);
        integer element2 = Int(Elem[operand2, e, esize], unsigned);
        integer res = Min(element1, element2);
        Elem[results[r], e, esize] = res<esize-1:0>;

for r = 0 to nreg-1
    Z[dn+r, VL] = results[r];