sqdmulh
Multi-vector Signed Saturating Doubling Multiply High
SQDMULH { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }
Saturating doubling multiply high on 2 or 4 vectors.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
11000001
31:24
size
23:22
1
21
Zm
20:17
0101101
16:10
00000
9:5
Zdn
4:1
0
0
Related
More in SME2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5F00C000 | SQDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>] | A64 | 01 | 0 | 11111 | size | L | M | Rm | 110 | 0 | H | 0 | Rn | Rd | ||
| 0x0F00C000 | SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] | A64 | 0 | Q | 0 | 01111 | size | L | M | Rm | 110 | 0 | H | 0 | Rn | Rd | ||
| 0x5E20B400 | SQDMULH <V><d>, <V><n>, <V><m> | A64 | 01 | 0 | 11110 | size | 1 | Rm | 10110 | 1 | Rn | Rd | ||
| 0x0E20B400 | SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 10110 | 1 | Rn | Rd | ||
| 0xC120A400 | SQDMULH { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101001 | 00000 | Zdn | 0 | ||
| 0xC120AC00 | SQDMULH { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101011 | 00000 | Zdn | 0 | 0 | ||
| 0xC120B400 | SQDMULH { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } | A64 | 11000001 | size | 1 | Zm | 0101101 | 00000 | Zdn | 0 | ||
| 0xC120BC00 | SQDMULH { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } | A64 | 11000001 | size | 1 | Zm | 00101111 | 00000 | Zdn | 0 | 0 | ||
| 0x04207000 | SQDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 1 | Zm | 01110 | 0 | Zn | Zd | ||
| 0x4420F000 | SQDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>] | A64 | 01000100 | 0 | i3h | 1 | i3l | Zm | 11110 | 0 | Zn | Zd | ||
| 0x44A0F000 | SQDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>] | A64 | 01000100 | 1 | 0 | 1 | i2 | Zm | 11110 | 0 | Zn | Zd | ||
| 0x44E0F000 | SQDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>] | A64 | 01000100 | 1 | 1 | 1 | i1 | Zm | 11110 | 0 | Zn | Zd |
Description
Multiply then double the corresponding signed elements of the two or four first and second source vectors, and destructively place the most significant half of the result in the corresponding elements of the two or four first source vectors. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1))-1. This instruction is unpredicated.
Operation
CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
array [0..3] of bits(VL) results;
for r = 0 to nreg-1
bits(VL) operand1 = Z[dn+r, VL];
bits(VL) operand2 = Z[m+r, VL];
for e = 0 to elements-1
integer element1 = SInt(Elem[operand1, e, esize]);
integer element2 = SInt(Elem[operand2, e, esize]);
integer res = 2 * element1 * element2;
Elem[results[r], e, esize] = SignedSat(res >> esize, esize);
for r = 0 to nreg-1
Z[dn+r, VL] = results[r];