ARM Opcode Map
Reverse lookup instructions by their hexadecimal encoding.
| Opcode | Mnemonic | Syntax | Format | Name |
|---|---|---|---|---|
| 0x01A00F90 | strexd | STREXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] | Load/Store Excl | Store Register Exclusive Double (A32) |
| 0x01E00F90 | strexh | STREXH<c> <Rd>, <Rt>, [<Rn>] | Load/Store Excl | Store Register Exclusive Halfword (A32) |
| 0xE8C00F50 | strexh | STREXH <Rd>, <Rt>, [<Rn>] | Thumb Store Excl | Store Register Exclusive Halfword (Thumb) |
| 0x79000000 | strh | STRH <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Store Register Halfword (Immediate) |
| 0x78200800 | strh | STRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Store Register Halfword (Register) |
| 0xF8A00000 | strh.w | STRH.W <Rt>, [<Rn>, #<imm>] | Thumb Store | Store Register Halfword (Wide) |
| 0x002000B0 | strht | STRHT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | Store Register Halfword Unprivileged |
| 0x04200000 | strt | STRT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | Store Register Unprivileged |
| 0xB8000800 | sttr | STTR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Store Register (Unprivileged) |
| 0x38000800 | sttrb | STTRB <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Store Register Byte (Unprivileged) |
| 0x78000800 | sttrh | STTRH <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Store Register Halfword (Unprivileged) |
| 0xB8000000 | stur | STUR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Store Register (Unscaled) |
| 0x38000000 | sturb | STURB <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Store Register Byte (Unscaled) |
| 0x78000000 | sturh | STURH <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Store Register Halfword (Unscaled) |
| 0x88200000 | stxp | STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>] | Load/Store Excl | Store Exclusive Pair |
| 0x88007C00 | stxr | STXR <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Store Exclusive Register |
| 0x08007C00 | stxrb | STXRB <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Store Exclusive Register Byte |
| 0x48007C00 | stxrh | STXRH <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Store Exclusive Register Halfword |
| 0xD9E00800 | stz2g | STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | Store Allocation Tag and Zero (Two Granules) |
| 0xD9600800 | stzg | STZG <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | Store Allocation Tag and Zero |
| 0x4B200000 | sub | SUB <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing | Subtract (Extended Register) |
| 0x51000000 | sub | SUB <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing | Subtract (Immediate) |
| 0x4B000000 | sub | SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing | Subtract (Shifted Register) |
| 0x2E208400 | sub | SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Subtract (Integer) |
| 0x04010000 | sub | SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE Integer Subtract (Predicated) |
| 0x02400000 | sub | SUB{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | Subtract (A32) |
| 0xEBA00000 | sub.w | SUB.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | Subtract (Wide) |
| 0xD1800000 | subg | SUBG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> | Data Processing | Subtract with Tag |
| 0x9AC00000 | subp | SUBP <Xd>, <Xn|SP>, <Xm|SP> | Data Processing | Subtract Pointers |
| 0xBAC00000 | subps | SUBPS <Xd>, <Xn|SP>, <Xm|SP> | Data Processing | Subtract Pointers, Setting Flags |
| 0x6B200000 | subs | SUBS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing | Subtract and Set Flags (Extended) |
| 0x71000000 | subs | SUBS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing | Subtract and Set Flags (Immediate) |
| 0x6B000000 | subs | SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing | Subtract and Set Flags (Shifted) |
| 0x02500000 | subs | SUBS PC, LR, #<imm> | Data Proc | Subtract and Return (A32) |
| 0x0F00F000 | sudot | SUDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>[<index>] | NEON 3-Reg | Signed-Unsigned Dot Product (NEON) |
| 0x05313800 | sunpkhi | SUNPKHI <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE Signed Unpack High |
| 0x05303800 | sunpklo | SUNPKLO <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE Signed Unpack Low |
| 0xD4000001 | svc | SVC #<imm> | Exception | Supervisor Call |
| 0xDF00 | svc | SVC #<imm> | Thumb System | Supervisor Call (Thumb) |
| 0x0F000000 | svc | SVC<c> #<imm> | System | Supervisor Call (A32) |
| 0xB8208000 | swp | SWP <Ws>, <Wt>, [<Xn|SP>] | Atomic | Swap Word |
| 0xB8208000 | swp | SWP<c> <Rt>, <Rt2>, [<Rn>] | Load/Store | Swap (A32) |
| 0x06A00070 | sxtab | SXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | Signed Extend and Add Byte |
| 0x06800070 | sxtab16 | SXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | Signed Extend and Add Byte 16 |
| 0x06B00070 | sxtah | SXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | Signed Extend and Add Halfword |
| 0xB240 | sxtb | SXTB <Rd>, <Rm> | Thumb Data Proc | Signed Extend Byte (Thumb) |
| 0x06AF0070 | sxtb | SXTB<c> <Rd>, <Rm> {, <rotation>} | Data Proc | Signed Extend Byte (A32) |
| 0x13001C00 | sxtb | SXTB <Wd>, <Wn> | Bitfield | Sign Extend Byte |
| 0x068F0070 | sxtb16 | SXTB16<c> <Rd>, <Rm> {, <rotation>} | Data Proc | Signed Extend Byte 16 (A32) |
| 0xB200 | sxth | SXTH <Rd>, <Rm> | Thumb Data Proc | Signed Extend Halfword (Thumb) |
| 0x06BF0070 | sxth | SXTH<c> <Rd>, <Rm> {, <rotation>} | Data Proc | Signed Extend Halfword (A32) |
| 0x93407C00 | sxtw | SXTW <Xd>, <Wn> | Bitfield | Sign Extend Word |
| 0xD5080000 | sys | SYS #<op1>, Cn, Cm, #<op2> {, <Xt>} | System | System Instruction |
| 0xE8D0F000 | tbb | TBB [<Rn>, <Rm>] | Thumb Branch | Table Branch Byte |
| 0xE8D0F010 | tbh | TBH [<Rn>, <Rm>, LSL #1] | Thumb Branch | Table Branch Halfword |
| 0x0E000000 | tbl | TBL <Vd>.<T>, { <Vn>.16B, ... }, <Vm>.<T> | SIMD Table | Vector Table Lookup |
| 0x05203000 | tbl | TBL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE Table Lookup |
| 0x37000000 | tbnz | TBNZ <Wt|Xt>, #<imm>, <label> | Branch | Test Bit Not Zero |
| 0x36000000 | tbz | TBZ <Wt|Xt>, #<imm>, <label> | Branch | Test Bit Zero |
| 0xD503307F | tcommit | TCOMMIT | System | Transaction Commit |
| 0x03300000 | teq | TEQ<c> <Rn>, <Operand2> | Data Proc | Test Equivalence (A32) |
| 0xEA900F00 | teq.w | TEQ.W <Rn>, <Operand2> | Thumb2 Data Proc | Test Equivalence (Wide) |
| 0xD5088000 | tlbi | TLBI VMALLE1IS | System | TLB Invalidate (All) |
| 0xD5088000 | tlbi | TLBI VAE1, <Xt> | System | TLB Invalidate (VA) |
| 0xD5088000 | tlbi | TLBI <op> {, <Xt>} | System Alias | TLB Invalidate |
| 0xD50B72E0 | trcit | TRCIT <Xt> | System | Trace Instrumentation |
| 0x0E002800 | trn1 | TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | Vector Transpose 1 |
| 0x05207000 | trn1 | TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE Transpose 1 |
| 0x0E006800 | trn2 | TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | Vector Transpose 2 |
| 0x05207400 | trn2 | TRN2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE Transpose 2 |
| 0x0320F012 | tsb | TSB CSYNC | System Hint | Trace Synchronization Barrier (A32) |
| 0xD503225F | tsb | TSB CSYNC | System Hint | Trace Synchronization Barrier |
| 0x03100000 | tst | TST<c> <Rn>, <Operand2> | Data Proc | Test (A32) |
| 0xEA100F00 | tst.w | TST.W <Rn>, <Operand2> | Thumb2 Data Proc | Test (Wide) |
| 0xD5233060 | tstart | TSTART <Xd> | System | Transaction Start |
| 0xD5233160 | ttest | TTEST <Xd> | System | Transaction Test |
| 0x06500F10 | uadd16 | UADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | Unsigned Add 16 (A32) |
| 0x06500F90 | uadd8 | UADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | Unsigned Add 8 (A32) |
| 0x2E200000 | uaddl | UADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | Unsigned Add Long |
| 0x04012000 | uaddv | UADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE Unsigned Integer Add Reduction |
| 0x2E201000 | uaddw | UADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> | SIMD Three Register Diff | Unsigned Add Wide |
| 0x53000000 | ubfm | UBFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Unsigned Bitfield Move |
| 0x07E00050 | ubfx | UBFX<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | Unsigned Bit Field Extract (A32) |
| 0xF3C00000 | ubfx | UBFX <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | Unsigned Bit Field Extract (Thumb) |
| 0x6553A000 | ucvtf | UCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE Unsigned Integer Convert to Floating-Point |
| 0x1E230000 | ucvtf | UCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>} | FP Conversion | Unsigned Integer Convert to Floating-Point |
| 0xE7F000F0 | udf | UDF #<imm> | System | Undefined Instruction |
| 0xDE00 | udf | UDF #<imm> | Thumb System | Undefined Instruction (Thumb) |
| 0x04150000 | udiv | UDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE Unsigned Divide |
| 0x1AC00800 | udiv | UDIV <Wd>, <Wn>, <Wm> | Data Processing | Unsigned Divide |
| 0xFBB0F0F0 | udiv | UDIV <Rd>, <Rn>, <Rm> | Thumb Div | Unsigned Divide (Thumb) |
| 0x0730F010 | udiv | UDIV<c> <Rd>, <Rn>, <Rm> | Data Proc | Unsigned Divide (A32) |
| 0x44000400 | udot | UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | SVE Dot Product | SVE Unsigned Dot Product |
| 0x4400CC00 | udot | UDOT<c>.U8 <Qd>, <Qn>, <Qm> | NEON 3-Reg | Unsigned Dot Product (A32) |
| 0x2E009400 | udot | UDOT <Vd>.4S, <Vn>.16B, <Vm>.16B | NEON DotProd | Unsigned Dot Product (NEON) |
| 0x44000400 | udot | UDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B | SME2 DotProd | Unsigned Dot Product (Multi-vector) |
| 0x06700F10 | uhadd16 | UHADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | Unsigned Halving Add 16 |
| 0x06700F90 | uhadd8 | UHADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | Unsigned Halving Add 8 |
| 0x06700F70 | uhsub16 | UHSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | Unsigned Halving Subtract 16 |
| 0x06700FF0 | uhsub8 | UHSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | Unsigned Halving Subtract 8 |