Home / ARM / Table

ARM Opcode Map

Reverse lookup instructions by their hexadecimal encoding.

← Back to List
Opcode Mnemonic Syntax Format Name
0xF3B00C00 vdup VDUP<c>.<dt> <Qd>, <Dm[x]> NEON Scalar Vector Duplicate (Scalar)
0xF3000110 veor VEOR<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Exclusive OR
0xF2B00000 vext VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm> NEON Extract Vector Extract
0x0EA00B00 vfma VFMA<c>.F64 <Qd>, <Qn>, <Qm> VFP Arith Vector Fused Multiply Accumulate (Double)
0xF2000C10 vfma VFMA<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Fused Multiply Accumulate
0x0EA00B40 vfms VFMS<c>.F64 <Qd>, <Qn>, <Qm> VFP Arith Vector Fused Multiply Subtract (Double)
0xF2200C10 vfms VFMS<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Fused Multiply Subtract
0x0E900A40 vfnma VFNMA<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Fused Negated Multiply Accumulate
0x0E900A00 vfnms VFNMS<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Fused Negated Multiply Subtract
0xF2000040 vhadd VHADD<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Halving Add
0xF2000200 vhsub VHSUB<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Halving Subtract
0x0EB90BC0 vjcvt VJCVT<c>.S32.F64 <Sd>, <Dm> VFP Convert Vector Javascript Convert (A32)
0xF4A0000D vld1 VLD1<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (Single Element)
0xF4A0010D vld2 VLD2<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (2-Element Structure)
0xF4A0020D vld3 VLD3<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (3-Element Structure)
0xF4A0030D vld4 VLD4<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (4-Element Structure)
0x0C900A00 vldm VLDM<c><mode> <Rn>{!}, <list> VFP Load Multiple Vector Load Multiple (VFP)
0x0D100A00 vldr VLDR<c> <Sd>, [<Rn>, #+/-<imm>] VFP Load Vector Load Register (VFP)
0xF2000600 vmax VMAX<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Maximum
0xFE800A00 vmaxnm VMAXNM<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Maximum Number
0xFE800B00 vmaxnm VMAXNM<c>.F64 <Dd>, <Dn>, <Dm> VFP Misc Vector Maximum Number (Double)
0xF2000610 vmin VMIN<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Minimum
0xFE800A40 vminnm VMINNM<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Minimum Number
0xFE800B40 vminnm VMINNM<c>.F64 <Dd>, <Dn>, <Dm> VFP Misc Vector Minimum Number (Double)
0x0E000A00 vmla VMLA<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Multiply Accumulate (VFP)
0xF2000900 vmla VMLA<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Multiply Accumulate
0x0E000A40 vmls VMLS<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Multiply Subtract (VFP)
0xF2200D50 vmls VMLS<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Multiply Subtract
0xFC000C40 vmmla VMMLA<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Matrix Multiply Accumulate (A32)
0x0EB00B40 vmov VMOV<c>.F64 <Dd>, <Dm> VFP Move Vector Move (Double)
0x0C400B10 vmov VMOV<c> <Rt>, <Rt2>, <Dm> VFP Transfer Vector Move (Double <-> 2xGPR)
0x0EB00A40 vmov VMOV<c>.F32 <Sd>, <Sm> VFP Move Vector Move (Register)
0x0E000A10 vmov VMOV<c> <Sn>, <Rt> VFP Transfer Vector Move (Core <-> VFP)
0xF2800010 vmov VMOV<c>.<dt> <Qd>, #<imm> NEON Imm Vector Move (Immediate)
0xF2800A10 vmovl VMOVL<c>.<dt> <Qd>, <Dm> NEON 2-Reg Vector Move Long
0xF3B20200 vmovn VMOVN<c>.<dt> <Dd>, <Qm> NEON 2-Reg Vector Move Narrow
0x0EF00A10 vmrs VMRS<c> <Rt>, <spec_reg> VFP System Move VFP System Register to Register
0x0EE00A10 vmsr VMSR<c> <spec_reg>, <Rt> VFP System Move Register to VFP System Register
0x0E200A00 vmul VMUL<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Multiply (VFP)
0xF2000910 vmul VMUL<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Multiply
0xF2800C00 vmull VMULL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Multiply Long
0xF3B00580 vmvn VMVN<c> <Qd>, <Qm> NEON 2-Reg Vector Move NOT
0x0EB10B40 vneg VNEG<c>.F64 <Dd>, <Dm> VFP Unary Vector Negate (Double)
0x0EB10A40 vneg VNEG<c>.F32 <Sd>, <Sm> VFP Unary Vector Negate (VFP)
0xF3B10380 vneg VNEG<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Negate
0x0E200A40 vnmul VNMUL<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Negated Multiply (VFP)
0xF2300150 vorn VORN<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector OR NOT
0xF2200110 vorr VORR<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Logical OR
0xF3B00600 vpadal VPADAL<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Pairwise Add and Accumulate Long
0xF2000B10 vpadd VPADD<c>.<dt> <Dd>, <Dn>, <Dm> NEON 3-Reg Vector Pairwise Add
0xF3B00200 vpaddl VPADDL<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Pairwise Add Long
0xF2000A00 vpmax VPMAX<c>.<dt> <Dd>, <Dn>, <Dm> NEON 3-Reg Vector Pairwise Maximum
0xF2000A10 vpmin VPMIN<c>.<dt> <Dd>, <Dn>, <Dm> NEON 3-Reg Vector Pairwise Minimum
0x0CBD0A00 vpop VPOP <list> VFP Load Multiple Vector Pop (VFP)
0x0D2D0A00 vpush VPUSH <list> VFP Store Multiple Vector Push (VFP)
0xF2000010 vqadd VQADD<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Add
0xF2800900 vqdmlal VQDMLAL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Saturating Doubling Multiply Accumulate Long
0xF2800B00 vqdmlsl VQDMLSL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Saturating Doubling Multiply Subtract Long
0xF2000B00 vqdmulh VQDMULH<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Doubling Multiply High
0xF2800D00 vqdmull VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Saturating Doubling Multiply Long
0xF3000B40 vqrdmulh VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Rounding Doubling Multiply High
0xF2000510 vqrshl VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Saturating Rounding Shift Left
0xF3B20280 vqrshrn VQRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Saturating Rounding Shift Right Narrow
0xF2000450 vqshl VQSHL<c>.<dt> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Saturating Shift Left (Register)
0xF2800710 vqshl VQSHL<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Left (Immediate)
0xF3800650 vqshlu VQSHLU<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Left Unsigned
0xF2800910 vqshr VQSHR<c>.U<size> <Qd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Right (Unsigned)
0xF2800910 vqshrn VQSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Right Narrow
0xF2000210 vqsub VQSUB<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Subtract
0xF3800400 vraddhn VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm> NEON 3-Reg Vector Rounding Add High Narrow
0xF3B30440 vrecpe VRECPE<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reciprocal Estimate
0xF2000F10 vrecps VRECPS<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Reciprocal Step
0xF3B00100 vrev16 VREV16<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reverse 16
0xF3B00080 vrev32 VREV32<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reverse 32
0xF3B00000 vrev64 VREV64<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reverse 64
0xFEB80A40 vrinta VRINTA<c>.F32 <Qd>, <Qm> NEON 2-Reg Vector Round Floating-Point (Nearest)
0xFEBB0A40 vrintm VRINTM<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Minus Infinity)
0xFEBB0B40 vrintm VRINTM<c>.F64 <Dd>, <Dm> VFP Unary Vector Round Floating-Point Double (Minus Infinity)
0xFEB90A40 vrintn VRINTN<c>.F32 <Qd>, <Qm> NEON 2-Reg Vector Round Floating-Point (Nearest Even)
0xFEBA0A40 vrintp VRINTP<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Plus Infinity)
0xFEBA0B40 vrintp VRINTP<c>.F64 <Dd>, <Dm> VFP Unary Vector Round Floating-Point Double (Plus Infinity)
0x0EB60A40 vrintr VRINTR<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Current)
0x0EB70A40 vrintx VRINTX<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Exact)
0x0EB60AC0 vrintz VRINTZ<c>.F32 <Qd>, <Qm> NEON 2-Reg Vector Round Floating-Point (Zero)
0xF2000500 vrshl VRSHL<c>.<dt> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Rounding Shift Left
0xF2800210 vrshr VRSHR<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Rounding Shift Right
0xF3B20200 vrshrn VRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Rounding Shift Right Narrow
0xF3B304C0 vrsqrte VRSQRTE<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reciprocal Square Root Estimate
0xF2200F10 vrsqrts VRSQRTS<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Reciprocal Square Root Step
0xF2800310 vrsra VRSRA<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Rounding Shift Right and Accumulate
0xF3800600 vrsubhn VRSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> NEON 3-Reg Vector Rounding Subtract High Narrow
0xFE000A00 vsel VSEL<cond>.F32 <Sd>, <Sn>, <Sm> VFP Misc Vector Select
0xFE000B00 vsel VSEL<cond>.F64 <Dd>, <Dn>, <Dm> VFP Misc Vector Select (Double)
0xF2800510 vshl VSHL<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Left (Immediate)
0xF2800010 vshr VSHR<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Right (Immediate)
0xF2800810 vshrn VSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Shift Right Narrow
0xF3800550 vsli VSLI<c>.<size> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Left and Insert
0xFC200C40 vsmmla VSMMLA<c>.S8 <Qd>, <Qn>, <Qm> NEON MatMul Vector Signed Int8 Matrix Multiply (A32)
0x0EB10BC0 vsqrt VSQRT<c>.F64 <Dd>, <Dm> VFP Unary Vector Square Root (Double)
0x0EB10AC0 vsqrt VSQRT<c>.F32 <Sd>, <Sm> VFP Unary Vector Square Root (VFP)