ARM Instructions
1145 instructions - showing 100 per page, page 10 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| umaal | UMAAL<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Calculates (Rn * Rm) + RdLo + RdHi -> 64-bit result. |
| umaddl | UMADDL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Multiplies two 32-bit regs, adds to 64-bit reg (Unsigned). |
| umax | UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines maximum unsigned value per element. |
| umax | UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns larger unsigned integer per element. |
| umaxv | UMAXV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds max unsigned element in vector. |
| umin | UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines minimum unsigned value per element. |
| umin | UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns smaller unsigned integer per element. |
| uminv | UMINV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds min unsigned element in vector. |
| uminv | UMINV <V><d>, <Vn>.<T> | SIMD Across Lane | NEON (SIMD) | Finds the minimum unsigned value across the vector. |
| umlal | UMLAL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Unsigned Multiply Accumulate (64-bit result). |
| umlal | UMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (Base) | Unsigned (Rn * Rm) + 64-bit Accumulator. |
| umlal | UMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies unsigned narrow vectors and adds to wide destination. |
| ummla | UMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Performs 2x2 matrix multiplication on Unsigned Int8 tiles. |
| umsubl | UMSUBL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Calculates (Xa - (Wn * Wm)) (Unsigned 64-bit). |
| umulh | UMULH <Xd>, <Xn>, <Xm> | Data Processing | Base | Multiplies two 64-bit registers, keeps high 64 bits (Unsigned). |
| umull | UMULL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Unsigned Multiply (64-bit result). |
| umull | UMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (Base) | Unsigned (Rn * Rm) -> 64-bit Result. |
| umull | UMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies unsigned narrow vectors, producing wider result. |
| uqadd | UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds unsigned integers with saturation. |
| uqadd16 | UQADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating add of 2 halfwords. |
| uqadd8 | UQADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating add of 4 bytes. |
| uqsub | UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts unsigned integers with saturation. |
| uqsub16 | UQSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating subtract of 2 halfwords. |
| uqsub8 | UQSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating subtract of 4 bytes. |
| uqxtn | UQXTN <Vd>.<Tb>, <Vn>.<Ta> | SIMD Shift Imm | NEON (SIMD) | Reads wide unsigned elements, saturates, and narrows. |
| urecpe | URECPE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Estimates reciprocal for unsigned integers. |
| usad8 | USAD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Computes sum of absolute differences of bytes (Video Codec). |
| usada8 | USADA8<c> <Rd>, <Rn>, <Rm>, <Ra> | SIMD Integer | A32 (DSP) | USAD8 plus accumulator. |
| usat | USAT<c> <Rd>, #<imm>, <Rm> {, <shift>} | Data Proc | A32 (DSP) | Saturates an unsigned value to a specified bit width. |
| usat16 | USAT16<c> <Rd>, #<imm>, <Rm> | Data Proc | A32 (DSP) | Saturates two unsigned 16-bit values. |
| usdot | USDOT<c>.S8 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (DotProd) | Dot product of unsigned and signed integers. |
| usdot | USDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Dot product of Unsigned Int8 and Signed Int8. |
| ushr | USHR <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts elements right (logical). |
| usmmla | USMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Matrix multiply Unsigned Int8 with Signed Int8. |
| usra | USRA <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Logical right shift and add to destination. |
| usub16 | USUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel sub of two unsigned 16-bit halfwords. |
| usubl | USUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Subtracts unsigned narrow vectors, producing wider result. |
| uunpkhi | UUNPKHI <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and zero-extends upper half of vector elements. |
| uunpklo | UUNPKLO <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and zero-extends lower half of vector elements. |
| uxtab | UXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends a byte and adds to Rn. |
| uxtab16 | UXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends two bytes and adds to two halfwords. |
| uxtah | UXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends a halfword and adds to Rn. |
| uxtb | UXTB <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Zero-extends byte to word (Thumb). |
| uxtb | UXTB<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Zero-extends the low byte to 32-bits. |
| uxtb16 | UXTB16<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends two bytes to two halfwords. |
| uxth | UXTH <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Zero-extends halfword to word (Thumb). |
| uxth | UXTH<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Zero-extends the low halfword to 32-bits. |
| uzp1 | UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | De-interleaves lower halves (Selects odd elements). |
| uzp1 | UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Selects even elements from concatenated vectors. |
| uzp2 | UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | De-interleaves upper halves (Selects even elements). |
| uzp2 | UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Selects odd elements from concatenated vectors. |
| vaba | VABA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference and adds to accumulator. |
| vabal | VABAL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference of narrow elements and adds to wide acc. |
| vabd | VABD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference between elements. |
| vabdl | VABDL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference of narrow elements to wide result. |
| vabs | VABS<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Absolute value of double-precision register. |
| vabs | VABS<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Calculates absolute value. |
| vabs | VABS<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Calculates absolute value of integer/float elements. |
| vacge | VACGE<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares absolute values (|Vn| >= |Vm|). |
| vacgt | VACGT<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares absolute values (|Vn| > |Vm|). |
| vadd | VADD<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Adds two floating-point values. |
| vadd | VADD<c>.F64 <Dd>, <Dn>, <Dm> | VFP Arith | VFP (Float) | Adds two double-precision floating-point values. |
| vadd | VADD<c>.I<size> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds integer elements of two vectors. |
| vaddhn | VADDHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds 2N-bit elements, selects high N-bits for result. |
| vaddl | VADDL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Adds N-bit elements, producing 2N-bit results. |
| vaddw | VADDW<c>.<dt> <Qd>, <Qn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Adds N-bit vector to 2N-bit vector. |
| vand | VAND<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise AND of two vectors. |
| vbfcvt | VBFCVT<c>.BF16.F32 <Qd>, <Qm> | NEON BFloat16 | NEON (BFloat16) | Converts Float32 to BFloat16. |
| vbfmmla | VBFMMLA<c>.BF16 <Qd>, <Qn>, <Qm> | NEON BFloat16 | NEON (BFloat16) | BFloat16 matrix multiply-accumulate. |
| vbic | VBIC<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | ANDs Vd with NOT of Vm (Vd & ~Vm). |
| vbif | VBIF<c> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Inserts bits from Vm into Vd where Vn (mask) is 0. |
| vbit | VBIT<c> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Inserts bits from Vm into Vd where Vn (mask) is 1. |
| vbsl | VBSL<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Selects bits from Vn or Vm based on Vd (mask). |
| vcadd | VCADD<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> | NEON Complex | NEON (Complex) | Complex integer addition with rotation (NEON). |
| vceq | VCEQ<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Sets destination bits to all 1s if elements equal, else 0s. |
| vcge | VCGE<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares elements (>=) and sets result mask. |
| vcgt | VCGT<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares elements (>) and sets result mask. |
| vcle | VCLE<c>.<dt> <Qd>, <Qn>, <Qm> | NEON Alias | NEON (SIMD) | Compares elements (<=). Alias for VCGE with swapped operands. |
| vcls | VCLS<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Counts number of consecutive sign bits. |
| vclt | VCLT<c>.<dt> <Qd>, <Qn>, <Qm> | NEON Alias | NEON (SIMD) | Compares elements (<). Alias for VCGT with swapped operands. |
| vclz | VCLZ<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Counts number of consecutive zeros. |
| vcmla | VCMLA<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> | NEON Complex | NEON (Complex) | Complex integer multiply-accumulate with rotation. |
| vcmp | VCMP<c>.F32 <Sd>, #0.0 | VFP Compare | VFP (Float) | Compares a floating-point value with #0.0. |
| vcmp | VCMP<c>.F64 <Dd>, <Dm> | VFP Compare | VFP (Float) | Compares two double-precision values. |
| vcmp | VCMP<c>.F32 <Sd>, <Sm> | VFP Compare | VFP (Float) | Compares two floating-point values. |
| vcmpe | VCMPE<c>.F32 <Sd>, <Sm> | VFP Compare | VFP (Float) | Compares values and raises exception on NaN. |
| vcnt | VCNT<c>.8 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Population count (number of 1s) per byte. |
| vcvt | VCVT<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits> | VFP Convert | VFP (Float) | Converts between floating-point and fixed-point. |
| vcvt | VCVT<c>.<Td>.<Tm> <Sd>, <Sm> | VFP Convert | VFP (Float) | Converts float to signed/unsigned integer. |
| vcvta | VCVTA<c>.<dt>.F64 <Sd>, <Dm> | VFP Convert | VFP (Float) | Converts double to integer, rounding to nearest. |
| vcvta | VCVTA<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding to nearest. |
| vcvtb | VCVTB<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Bottom half). |
| vcvtm | VCVTM<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding towards -Inf (Floor). |
| vcvtn | VCVTN<c>.<dt>.F64 <Sd>, <Dm> | VFP Convert | VFP (Float) | Converts double to integer, rounding to nearest even. |
| vcvtn | VCVTN<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding to nearest even. |
| vcvtp | VCVTP<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding towards +Inf (Ceil). |
| vcvtt | VCVTT<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Top half). |
| vdiv | VDIV<c>.F64 <Dd>, <Dn>, <Dm> | VFP Arith | VFP (Float) | Divides two double-precision registers. |
| vdiv | VDIV<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Divides two floating-point values. |
| vdot | VDOT<c>.BF16 <Qd>, <Qn>, <Qm> | NEON BFloat16 | NEON (BFloat16) | BFloat16 dot product to float32 accumulator. |