ARM Instructions
1145 instructions - showing 100 per page, page 8 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| smaxv | SMAXV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds max signed element in vector. |
| smaxv | SMAXV <V><d>, <Vn>.<T> | SIMD Across Lane | NEON (SIMD) | Finds the maximum signed value across the vector. |
| smc | SMC<c> #<imm> | System | A32 (System) | Calls the Secure Monitor (EL3). |
| smc | SMC #<imm> | Thumb System | A32 (Security) | Calls the Secure Monitor (EL3) from Thumb state. |
| smin | SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines minimum signed value per element. |
| smin | SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns smaller signed integer per element. |
| sminv | SMINV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds min signed element in vector. |
| smlabb | SMLABB<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.B) into Ra. |
| smlabt | SMLABT<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.T) into Ra. |
| smlad | SMLAD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Dual multiply add + accumulate. |
| smlal | SMLAL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Signed Multiply Accumulate (64-bit result). |
| smlal | SMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies signed narrow vectors and adds to wide destination. |
| smlalbb | SMLALBB<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.B) into 64-bit pair. |
| smlalbt | SMLALBT<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.T) into 64-bit pair. |
| smlald | SMLALD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Dual multiply add + 64-bit accumulate. |
| smlaltb | SMLALTB<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.B) into 64-bit pair. |
| smlaltt | SMLALTT<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.T) into 64-bit pair. |
| smlatb | SMLATB<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.B) into Ra. |
| smlatt | SMLATT<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.T) into Ra. |
| smlawb | SMLAWB<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Performs SMULWB and adds to accumulator. |
| smlawt | SMLAWT<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Performs SMULWT and adds to accumulator. |
| smlsd | SMLSD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Dual multiply subtract + accumulate. |
| smlsld | SMLSLD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Dual multiply subtract + 64-bit accumulate. |
| smmla | SMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Performs 2x2 matrix multiplication on Signed Int8 tiles. |
| smmla | SMMLA{R}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | SMMUL + Accumulate. |
| smmul | SMMUL{R}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies and returns the top 32-bits of the 64-bit result. |
| smsubl | SMSUBL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Calculates (Xa - (Wn * Wm)) (64-bit result). |
| smuad | SMUAD{X}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Performs two 16x16 multiplies and adds results (Top*Top + Bot*Bot). |
| smulbb | SMULBB<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies bottom 16 bits of Rn and Rm. |
| smulbt | SMULBT<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies bottom 16 bits of Rn and top 16 bits of Rm. |
| smulh | SMULH <Xd>, <Xn>, <Xm> | Data Processing | Base | Multiplies two 64-bit registers, keeps high 64 bits. |
| smull | SMULL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Signed Multiply (64-bit result). |
| smull | SMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies signed narrow vectors, producing wider result. |
| smultb | SMULTB<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies top 16 bits of Rn and bottom 16 bits of Rm. |
| smultt | SMULTT<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies top 16 bits of Rn and top 16 bits of Rm. |
| smulwb | SMULWB<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies 32-bit Rn by bottom 16-bits of Rm, takes top 32-bits of result. |
| smulwt | SMULWT<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies 32-bit Rn by top 16-bits of Rm, takes top 32-bits of result. |
| smusd | SMUSD{X}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Performs two 16x16 multiplies and subtracts results. |
| splice | SPLICE <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T> | SVE Permute | SVE | Splices two vectors based on the last active element of the first. |
| sqadd | SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds signed integers with saturation. |
| sqsub | SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts signed integers with saturation. |
| sqxtn | SQXTN <Vd>.<Tb>, <Vn>.<Ta> | SIMD Shift Imm | NEON (SIMD) | Reads wide elements, saturates, and narrows. |
| sri | SRI <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts source right and inserts into destination. |
| srs | SRS<c> SP{!}, #<mode> | System | A32 (System) | Stores LR and SPSR to the stack of a specific mode. |
| ssat | SSAT<c> <Rd>, #<imm>, <Rm> {, <shift>} | Data Proc | A32 (DSP) | Saturates a signed value to a specified bit width. |
| ssat16 | SSAT16<c> <Rd>, #<imm>, <Rm> | Data Proc | A32 (DSP) | Saturates two signed 16-bit values. |
| ssbb | SSBB | System Hint | A32 (v8.0) | Prevents speculative loads bypassing earlier stores (v8.0). |
| sshr | SSHR <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts elements right (arithmetic/sign-extending). |
| ssra | SSRA <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Arithmetic right shift and add to destination. |
| ssub16 | SSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel sub of two signed 16-bit halfwords. |
| ssubl | SSUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Subtracts signed narrow vectors, producing wider result. |
| st1 | ST1 { <Vt>.<T>, ... }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores one element structure from 1-4 registers to memory. |
| st1b | ST1B { <Zt>.B }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active bytes from vector to memory. |
| st1d | ST1D { <Zt>.D }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active doublewords from vector to memory. |
| st1h | ST1H { <Zt>.H }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active halfwords from vector to memory. |
| st1w | ST1W { <Zt>.S }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active words from vector to memory. |
| st1w | ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, SXTW #<shift>] | SVE Scatter | SVE | Stores words to non-contiguous addresses. |
| st2 | ST2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores two-element structures from two registers to memory (Interleave). |
| st2g | ST2G <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag to two memory granules. |
| st3 | ST3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores three-element structures from three registers (Interleave RGB). |
| st4 | ST4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores four-element structures from four registers (Interleave RGBA). |
| st64b | ST64B <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Stores a 64-byte block of data atomically. |
| st64bv | ST64BV <Ws>, <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Stores 64 bytes atomically and returns status (Success/Fail). |
| st64bv0 | ST64BV0 <Ws>, <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Stores 64 bytes (eliding the first 8 bytes as zero) and returns status. |
| stc | STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Stores coprocessor contents to memory. |
| stc2 | STC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Stores coprocessor contents to memory (Extension encoding). |
| stg | STG <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag to memory. |
| stg | STG <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag to memory. |
| stgp | STGP <Xt>, <Xt2>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores Tag and two 64-bit data values. |
| stl | STL<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Stores a word with Release semantics. |
| stlex | STLEX<c> <Rd>, <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Stores a word with Release Exclusive semantics. |
| stlexb | STLEXB<c> <Rd>, <Rt>, [<Rn>] | Store Excl | A32 (Atomic) | Stores a byte with Release semantics if exclusive. |
| stlexd | STLEXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] | Store Excl | A32 (Atomic) | Stores a doubleword with Release semantics if exclusive. |
| stlexh | STLEXH<c> <Rd>, <Rt>, [<Rn>] | Store Excl | A32 (Atomic) | Stores a halfword with Release semantics if exclusive. |
| stlr | STLR <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Stores a word with Release semantics. |
| stlrb | STLRB <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Stores a byte with Release semantics. |
| stlrh | STLRH <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Stores a halfword with Release semantics. |
| stlxr | STLXR <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a word with Release Exclusive semantics. |
| stlxrb | STLXRB <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a byte with Release Exclusive semantics. |
| stlxrh | STLXRH <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a halfword with Release Exclusive semantics. |
| stm | STM <Rn>!, <registers> | Thumb Store Multiple | T32 (Base) | Store multiple registers (Thumb 16-bit). |
| stm | STM<mode><c> <Rn>{!}, <registers> | Store Multiple | A32 (Base) | Stores multiple registers to memory. |
| stm.w | STM.W <Rn>{!}, <registers> | Thumb Store Multiple | T32 (Thumb2) | Thumb-2 32-bit Store Multiple. |
| stnp | STNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Stores two registers, hinting non-temporal data. |
| stp | STP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Floating Point | Stores two floating-point/SIMD registers. |
| stp | STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Stores two 32-bit registers. |
| stp | STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Stores two 64-bit registers. |
| str | STR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] | Load/Store | Floating Point | Stores a floating-point/SIMD register to memory. |
| str | STR <Wt>, [<Xn|SP>, #<pimm>] | Load/Store Imm | Base | Stores a register to memory (Immediate offset). |
| str | STR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store Reg | Base | Stores a register to memory (Register offset). |
| str | STR<c> <Rt>, [<Rn>, #+/-<imm>]{!} | Load/Store | A32 (Base) | Stores a word to memory. |
| str.w | STR.W <Rt>, [<Rn>, #<imm>] | Thumb Store | T32 (Thumb2) | Thumb-2 32-bit Store Word. |
| strb | STRB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Stores the low byte of a register. |
| strb | STRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Stores the low byte of a register using register offset. |
| strb.w | STRB.W <Rt>, [<Rn>, #<imm>] | Thumb Store | T32 (Thumb2) | Thumb-2 32-bit Store Byte. |
| strbt | STRBT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Stores a byte using User Mode permissions. |
| strd | STRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] | Thumb Store | A32 (Base) | Stores two words to memory (Thumb). |
| strex | STREX <Rd>, <Rt>, [<Rn>] | Thumb Store Excl | A32 (Atomic) | Stores word if exclusive monitor is open (Thumb). |
| strexb | STREXB<c> <Rd>, <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Stores a byte if address is still exclusive. |
| strexb | STREXB <Rd>, <Rt>, [<Rn>] | Thumb Store Excl | A32 (Atomic) | Stores byte exclusively (Thumb). |