ARM Instructions
1145 instructions - showing 100 per page, page 6 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| mrc | MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Reads a coprocessor register into a general-purpose register. |
| mrc2 | MRC2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Reads a coprocessor register into a general-purpose register (Extension encoding). |
| mrrc | MRRC<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Reads a coprocessor register into two general-purpose registers. |
| mrrc2 | MRRC2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Reads a coprocessor register into two registers (Extension encoding). |
| mrrs | MRRS <Xt>, <Xt+1>, <sysreg> | System | FEAT_SYSREG128 | Reads a 128-bit system register into two general-purpose registers. |
| mrs | MRS <Xt>, <system_reg> | System | System | Moves system register to general-purpose register. |
| mrs | MRS <Rd>, <banked_reg> | System | A32 (System) | Reads a banked register into a general-purpose register. |
| mrs | MRS <Rd>, <spec_reg> | Thumb System | A32 (System) | Read special register (Thumb). |
| mrs | MRS<c> <Rd>, <spec_reg> | System | A32 (System) | Reads CPSR or SPSR. |
| msr | MSR <system_reg>, <Xt> | System | System | Moves general-purpose register to system register. |
| msr | MSR <banked_reg>, <Rn> | System | A32 (System) | Writes to a banked register from a general-purpose register. |
| msr | MSR <spec_reg>, #<imm> | System | A32 (System) | Writes an immediate to a status register (A32). |
| msr | MSR <spec_reg>, #<imm> | Thumb System | T32 (System) | Writes an immediate to a status register (Thumb). |
| msr | MSR <spec_reg>, <Rn> | Thumb System | A32 (System) | Write special register (Thumb). |
| msr | MSR<c> <spec_reg>_<fields>, <Rn> | System | A32 (System) | Writes to CPSR or SPSR. |
| msrr | MSRR <sysreg>, <Xt>, <Xt+1> | System | FEAT_SYSREG128 | Writes two general-purpose registers into a 128-bit system register. |
| msub | MSUB <Wd>, <Wn>, <Wm>, <Wa> | Data Processing | Base | Calculates (Ra - (Rn * Rm)). |
| mul | MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies corresponding elements in two vectors. |
| mul | MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Multiplies two vectors under predicate. |
| mul | MUL{S}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (Base) | Multiplies two 32-bit values. |
| mvn | MVN <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Bitwise NOT of a vector. |
| mvn | MVN{S}<c> <Rd>, <Operand2> | Data Proc | A32 (Base) | Moves bitwise inverse of value. |
| mvn.w | MVN.W <Rd>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Move Inverse. |
| mvni | MVNI <Vd>.<T>, #<imm8> {, lsl #<shift>} | SIMD Modified Imm | NEON (SIMD) | Moves the inverse of an immediate value into every element. |
| neg | NEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Integer Unary | SVE | Negates integers. |
| neg | NEG <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Negates integer elements. |
| nop | NOP | System Alias | Base | Does nothing. Used for padding or timing. |
| nop | NOP | Thumb System | T32 (Base) | No op (Thumb 16-bit). |
| nop | NOP<c> | System | A32 (Base) | Does nothing. |
| not | NOT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Integer Unary | SVE | Inverts bits. |
| not | NOT <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Inverts all bits. (Alias for MVN). |
| orn | ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | ORs register with NOT of shifted register. |
| orn | ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | ORs Vd with NOT of Vm. |
| orn.w | ORN.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit OR NOT. |
| orr | ORR <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Base | ORs register with logical immediate. |
| orr | ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | ORs two registers. |
| orr | ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Bitwise OR of two vectors. |
| orr | ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise OR of two vectors under predicate. |
| orr | ORR{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Performs bitwise OR. |
| orr.w | ORR.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit OR. |
| orv | ORV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | ORs all active elements into a scalar. |
| pacda | PACDA <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a data pointer using Key A. |
| pacda | PACDA <Xd>, <Xn> | Data Processing | PAC (Security) | Signs a data address using Key A. |
| pacdb | PACDB <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a data pointer using Key B. |
| pacdb | PACDB <Xd>, <Xn> | Data Processing | PAC (Security) | Signs a data address using Key B. |
| pacga | PACGA <Xd>, <Xn>, <Xm> | Data Processing | PAC (Security) | Computes a pointer authentication code for an address and modifier. |
| pacia | PACIA <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a pointer in Xd using Key A and modifier Xm (or SP). |
| pacia | PACIA <Xd>, <Xn> | Data Processing | PAC (Security) | Signs an instruction address using Key A. |
| pacib | PACIB <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a pointer in Xd using Key B. |
| pacib | PACIB <Xd>, <Xn> | Data Processing | PAC (Security) | Signs an instruction address using Key B. |
| pfalse | PFALSE <Pd>.B | SVE Predicate | SVE | Clears all elements of the predicate register. |
| pfirst | PFIRST <Pd>.B, <Pg>, <Pn>.B | SVE Predicate | SVE | Sets destination predicate to true only at the first active element. |
| pkhbt | PKHBT<c> <Rd>, <Rn>, <Rm> {, LSL #<imm>} | Data Proc | A32 (DSP) | Combines bottom half of Rn with top half of shifted Rm. |
| pkhtb | PKHTB<c> <Rd>, <Rn>, <Rm> {, ASR #<imm>} | Data Proc | A32 (DSP) | Combines top half of Rn with bottom half of shifted Rm. |
| pld | PLD [<Rn>, #<imm>] | Load/Store | A32 (System) | Hints memory system to bring data into cache. |
| pldw | PLDW [<Rn>, #<imm>] | Load/Store | A32 (Base) | Hints memory system to bring data into cache for writing. |
| pldw | PLDW [<Rn>, #<imm>] | Thumb Load/Store | T32 (Thumb2) | Hints memory system to bring data into cache for writing (Thumb). |
| pli | PLI [<Rn>, #<imm>] | Load/Store | A32 (System) | Hints memory system to bring instructions into cache. |
| pmul | PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Performs polynomial multiplication over {0,1}. |
| pmull | PMULL <Vd>.1Q, <Vn>.1D, <Vm>.1D | Crypto | Crypto (AES) | Polynomial multiply long (NEON). |
| pmull | PMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (Crypto/SIMD) | Performs polynomial multiplication over {0,1} producing wide result (Used for GCM). |
| pnext | PNEXT <Pdn>.<T>, <Pg>, <Pdn>.<T> | SVE Predicate | SVE | Finds the next active predicate bit. |
| pop | POP <registers> | Thumb Load Multiple | T32 (Base) | Pop registers from stack (Thumb 16-bit). |
| pop | POP<c> <registers> | Load Multiple | A32 (Base) | Loads registers from stack (Alias for LDMIA SP!). |
| pop.w | POP.W <registers> | Thumb Load Multiple | T32 (Thumb2) | Thumb-2 32-bit Pop. |
| prfm | PRFM <prfop>, [<Xn|SP>, #<pimm>] | Load/Store Imm | Base | Signals the memory system to prefetch data into cache. |
| prfm | PRFM <prfop>, <label> | Load Literal | Base | Prefetches data from a PC-relative address. |
| prfm | PRFM <prfop>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store Reg | Base | Prefetches data using a register offset. |
| psb | PSB CSYNC | System Alias | Profiling | Synchronizes the statistical profiling unit. |
| pssbb | PSSBB | System Hint | A32 (v8.0) | Prevents speculation on physical resources (v8.0). |
| pssbb | PSSBB | System Hint | Base (v8.5) | Prevents speculation on physical resources. |
| ptest | PTEST <Pg>, <Pn>.B | SVE Predicate | SVE | Updates processor flags (NZCV) based on predicate state. |
| ptrue | PTRUE <Pd>.<T> {, <pattern>} | SVE Predicate | SVE | Sets elements of the predicate register to true (all active). |
| push | PUSH <registers> | Thumb Store Multiple | T32 (Base) | Push registers to stack (Thumb 16-bit). |
| push | PUSH<c> <registers> | Store Multiple | A32 (Base) | Stores registers to stack (Alias for STMDB SP!). |
| push.w | PUSH.W <registers> | Thumb Store Multiple | T32 (Thumb2) | Thumb-2 32-bit Push. |
| qadd | QADD<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Adds two values and saturates the result. |
| qadd16 | QADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating add of 2 signed halfwords. |
| qadd8 | QADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating add of 4 signed bytes. |
| qdadd | QDADD<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Doubles the second operand, adds to first, and saturates. |
| qdsub | QDSUB<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Doubles the second operand, subtracts from first, and saturates. |
| qsub | QSUB<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Subtracts two values and saturates the result. |
| qsub16 | QSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating subtract of 2 signed halfwords. |
| qsub8 | QSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating subtract of 4 signed bytes. |
| rbit | RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE Permute | SVE | Reverses bits in each element. |
| rbit | RBIT <Wd>, <Wn> | Data Processing | Base | Reverses the bit order in a register. |
| rbit | RBIT <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bits in a 32-bit register. |
| rbit | RBIT <Xd>, <Xn> | Data Processing | Base | Reverses the bit order in a 64-bit register. |
| rbit | RBIT<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Reverses bits in a 32-bit register. |
| rcwsswpp | RCWS <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Read Check Write with soft failure reporting (Translation Hardening). |
| rcwswpp | RCWSWPP <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Atomically swaps a 128-bit register pair with a checked descriptor in memory (Translation Hardening). |
| rcwswppa | RCWSWPPA <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Atomically swaps a 128-bit register pair with a checked descriptor in memory, with Acquire semantics (Translation Hardening). |
| rcwswppal | RCWSWPPAL <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Atomically swaps a 128-bit register pair with a checked descriptor in memory, with Acquire and Release semantics (Translation Hardening). |
| ret | RET {<Xn>} | Branch | Base | Branches to address in LR (or specified register). |
| rev | REV <Zd>.<T>, <Zn>.<T> | SVE Permute | SVE | Reverses the order of elements in the vector. |
| rev | REV <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Endian swap (Thumb). |
| rev | REV <Xd>, <Xn> | Data Processing | Base | Reverses byte order in a 64-bit register. |
| rev | REV <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bytes (Endian swap). |
| rev | REV <Wd>, <Wn> | Data Processing | Base | Reverses the byte order in a 32-bit register (Endianness swap). |
| rev | REV<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Reverses bytes (Endian swap). |