ARM Instructions
1145 instructions - showing 100 per page, page 4 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| fmls | FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies and subtracts from destination (Vd = Vd - Vn * Vm). |
| fmls | FMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> | SVE FP Ternary | SVE | Calculates (Zda - Zn * Zm) under predicate. |
| fmls | FMLS <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Fused multiply-subtract on half-precision vectors. |
| fmov | FMOV <Hd|Sd|Dd>, #<fimm> | FP Immediate | Floating Point | Moves a floating-point immediate into a scalar register. |
| fmov | FMOV <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Copies a value from one scalar FP register to another. |
| fmov | FMOV <Wd|Xd>, <Sn|Dn> | FP Conversion | Floating Point | Copies bits between a General-Purpose Register (W/X) and FP Register (S/D). |
| fmov | FMOV <Sd|Dd>, <Wn|Xn> | FP Conversion | Floating Point | Copies bits from a General-Purpose Register (W/X) to FP Register (S/D). |
| fmov | FMOV <Dd>, <Dn> | Float Data Proc | F.P. | Copies value between floating-point registers. |
| fmov | FMOV <Dd>, #<imm> | Float Imm | F.P. | Moves immediate value into floating-point register. |
| fmsub | FMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates (Vn * Vm) - Va. |
| fmul | FMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Multiplies two floating-point values. |
| fmul | FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies elements of floating-point vectors. |
| fmul | FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Multiplies floating-point elements under predicate. |
| fmul | FMUL <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Multiplies two half-precision floating-point vectors. |
| fmul | FMUL <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Multiplies two single-precision floating-point registers. |
| fmul | FMUL <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Multiplies two double-precision floating-point registers. |
| fneg | FNEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE | Negates floats. |
| fneg | FNEG <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Negates the value (flips sign bit). |
| fneg | FNEG <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Negates each element. |
| fneg | FNEG <Vd>.8H, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Negates half-precision vector. |
| fnmadd | FNMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates -((Vn * Vm) + Va). |
| fnmsub | FNMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates -((Vn * Vm) - Va). |
| fnmul | FNMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Calculates -(Vn * Vm). |
| frecpe | FRECPE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Estimates reciprocal (1/x) for floats. |
| frecps | FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Newton-Raphson step for reciprocal refinement. |
| frint32x | FRINT32X <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 32-bit integer, exact exception. |
| frint32z | FRINT32Z <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 32-bit integer towards zero. |
| frint64x | FRINT64X <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 64-bit integer, exact exception. |
| frint64z | FRINT64Z <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 64-bit integer towards zero. |
| frinta | FRINTA <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to nearest integral value (ties away from zero). |
| frinti | FRINTI <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value using current FPCR rounding mode. |
| frintm | FRINTM <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value towards minus infinity (Floor). |
| frintn | FRINTN <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value nearest, ties to even. |
| frintp | FRINTP <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value towards plus infinity (Ceil). |
| frintx | FRINTX <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value using current mode, raising Inexact exception. |
| frintz | FRINTZ <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value towards zero (Truncate). |
| frsqrte | FRSQRTE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Estimates reciprocal square root (1/sqrt(x)). |
| frsqrts | FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Newton-Raphson step for reciprocal square root refinement. |
| fsqrt | FSQRT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE | Calculates square root of floats. |
| fsqrt | FSQRT <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Calculates square root. |
| fsqrt | FSQRT <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Calculates square root for each element. |
| fsqrt | FSQRT <Vd>.8H, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Square root of half-precision vector. |
| fsub | FSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Subtracts two floating-point values. |
| fsub | FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts elements of floating-point vectors. |
| fsub | FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Subtracts floating-point elements under predicate. |
| fsub | FSUB <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Subtracts two half-precision floating-point vectors. |
| fsub | FSUB <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Subtracts two single-precision floating-point registers. |
| fsub | FSUB <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Subtracts two double-precision floating-point registers. |
| gcspopm | GCSPOPM | System | FEAT_GCS (Security) | Pops the value from the Guarded Control Stack into LR. |
| gcsss1 | GCSSS1 <Xt> | System | FEAT_GCS (Security) | First step to switch the GCS pointer. |
| gcsss2 | GCSSS2 <Xt> | System | FEAT_GCS (Security) | Second step to switch the GCS pointer. |
| gmi | GMI <Xd>, <Xn|SP>, <Xm> | Data Processing | MTE (Memory Tagging) | Calculates a mask of excluded tags (MTE). |
| hint | HINT #<imm> | System | Base | Provides a hint to the processor (e.g., NOP, YIELD). |
| hlt | HLT #<imm> | Exception | Base | Enters Halting debug mode. |
| hlt | HLT #<imm> | Thumb System | T32 (Thumb) | Enters halting debug state (Thumb encoding). |
| hlt | HLT #<imm> | System | A32 (Base) | Enters halting debug state (A32 encoding). |
| hvc | HVC #<imm> | Exception | System | Generates a Hypervisor Call exception to EL2. |
| hvc | HVC #<imm> | Thumb System | A32 (Virtualization) | Calls the Hypervisor (EL2) from Thumb state. |
| hvc | HVC #<imm> | System | A32 (System) | Calls the Hypervisor (EL2). |
| ic | IC <op> {, <Xt>} | System Alias | System | Performs instruction cache maintenance. |
| incb | INCB <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Increments a general-purpose register by the number of active bytes in the pattern. |
| incd | INCD <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Increments a register by the number of active doublewords. |
| incw | INCW <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Increments a register by the number of active words. |
| index | INDEX <Zd>.<T>, <Start>, <Step> | SVE Index | SVE | Generates a vector of indices: V[i] = Start + i * Step. |
| ins | INS <Vd>.<Ts>[<index>], <Rn> | SIMD Copy | NEON (SIMD) | Moves data from a GPR to a specific vector element. |
| insr | INSR <Zdn>.<T>, <R><m> | SVE Move | SVE | Inserts scalar into bottom of vector, shifting other elements up. |
| irg | IRG <Xd|SP>, <Xn|SP>{, <Xm>} | Data Processing | MTE (Memory Tagging) | Inserts a random Allocation Tag into a pointer (MTE). |
| isb | ISB {<option>} | System | Base | Flushes the pipeline and prefetches. |
| isb | ISB <option> | Thumb System | A32 (Base) | Instruction barrier (Thumb). |
| isb | ISB <option> | System | A32 (Base) | Flushes the pipeline. |
| it | IT{x{y{z}}} <cond> | Thumb IT | T32 (Thumb) | Makes up to 4 following instructions conditional (Thumb-only). |
| lasta | LASTA <Vd>.<T>, <Pg>, <Zn>.<T> | SVE Extract | SVE | Extracts element after last active (SIMD scalar destination). |
| lastb | LASTB <Vd>.<T>, <Pg>, <Zn>.<T> | SVE Extract | SVE | Extracts last active element (SIMD scalar destination). |
| ld1 | LD1 { <Vt>.<T>, ... }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads one element structure from memory into 1-4 registers. |
| ld1b | LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads bytes from memory into a vector under predicate control. |
| ld1d | LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads doublewords from memory into a vector under predicate control. |
| ld1h | LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads halfwords from memory into a vector under predicate control. |
| ld1r | LD1R { <Vt>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads one element and replicates it to all lanes of the vector. |
| ld1w | LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads words from memory into a vector under predicate control. |
| ld1w | LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, SXTW #<shift>] | SVE Gather | SVE | Loads words from non-contiguous addresses (Scatter-Gather). |
| ld2 | LD2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads two-element structures from memory into two registers (De-interleave). |
| ld2r | LD2R { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads 2 elements and replicates them to all lanes. |
| ld3 | LD3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads three-element structures (e.g., RGB) into three registers. |
| ld4 | LD4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads four-element structures (e.g., RGBA) into four registers. |
| ld64b | LD64B <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Loads a 64-byte block of data atomically (Accelerator support). |
| lda | LDA<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Loads a word with Acquire semantics. |
| ldadd | LDADD <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic add to memory, return old value. |
| ldaex | LDAEX<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Loads a word with Acquire Exclusive semantics. |
| ldaexb | LDAEXB<c> <Rt>, [<Rn>] | Load Excl | A32 (Atomic) | Loads a byte, acquires semantics, marks exclusive. |
| ldaexd | LDAEXD<c> <Rt>, <Rt2>, [<Rn>] | Load Excl | A32 (Atomic) | Loads a doubleword, acquires semantics, marks exclusive. |
| ldaexh | LDAEXH<c> <Rt>, [<Rn>] | Load Excl | A32 (Atomic) | Loads a halfword, acquires semantics, marks exclusive. |
| ldapr | LDAPR <Wt>, [<Xn|SP>] | Load/Store | Base (RCpc) | Loads a word with RCpc Acquire semantics. |
| ldaprb | LDAPRB <Wt>, [<Xn|SP>] | Load/Store | Base (RCpc) | Loads a byte with Release Consistency (process consistent) Acquire semantics. |
| ldaprh | LDAPRH <Wt>, [<Xn|SP>] | Load/Store | Base (RCpc) | Loads a halfword with RCpc Acquire semantics. |
| ldar | LDAR <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Loads a word with Acquire semantics. |
| ldarb | LDARB <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Loads a byte with Acquire semantics. |
| ldarh | LDARH <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Loads a halfword with Acquire semantics. |
| ldaxr | LDAXR <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a word with Acquire Exclusive semantics. |
| ldaxrb | LDAXRB <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a byte with Acquire Exclusive semantics. |
| ldaxrh | LDAXRH <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a halfword with Acquire Exclusive semantics. |