ARM Instructions
1145 instructions - showing 100 per page, page 5 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| ldc | LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Loads memory into a coprocessor. |
| ldc2 | LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Loads memory into a coprocessor (Extension encoding). |
| ldclr | LDCLR <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic bit clear (AND NOT) to memory. |
| ldeor | LDEOR <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic XOR to memory. |
| ldff1b | LDFF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads bytes speculatively; suppresses faults after the first active element. |
| ldff1d | LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads doublewords speculatively; suppresses faults after the first active element. |
| ldff1h | LDFF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads halfwords speculatively; suppresses faults after the first active element. |
| ldff1w | LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads words speculatively; suppresses faults after the first active element. |
| ldg | LDG <Xt>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Loads the Allocation Tag from memory. |
| ldm | LDM <Rn>!, <registers> | Thumb Load Multiple | T32 (Base) | Load multiple registers (Thumb 16-bit). |
| ldm | LDM<mode><c> <Rn>{!}, <registers> | Load Multiple | A32 (Base) | Loads multiple registers from memory (Stack pop). |
| ldm.w | LDM.W <Rn>{!}, <registers> | Thumb Load Multiple | T32 (Thumb2) | Thumb-2 32-bit Load Multiple. |
| ldnf1b | LDNF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads bytes without faulting; returns 0 if fault occurs. |
| ldnf1d | LDNF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads doublewords without faulting. |
| ldnf1h | LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads halfwords without faulting. |
| ldnf1w | LDNF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads words without faulting. |
| ldnp | LDNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Loads two words, hinting non-temporal data (no caching). |
| ldp | LDP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Floating Point | Loads two floating-point/SIMD registers. |
| ldp | LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> | Load/Store Pair | Base | Loads two words from memory. |
| ldp | LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> | Load/Store Pair | Base | Loads two 64-bit doublewords from memory. |
| ldpsw | LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Loads two words and sign-extends them to 64-bit. |
| ldr | LDR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] | Load/Store | Floating Point | Loads a floating-point/SIMD register from memory. |
| ldr | LDR <Wt>, [<Xn|SP>, #<pimm>] | Load/Store Imm | Base | Loads a word from memory (Immediate offset). |
| ldr | LDR <Wt>, <label> | Load Literal | Base | Loads a word from a PC-relative address. |
| ldr | LDR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store Reg | Base | Loads a word from memory (Register offset). |
| ldr | LDR<c> <Rt>, <label> | Load Literal | A32 (Base) | Loads a word from a label. |
| ldr | LDR <Rt>, <label> | Thumb Load | T32 (Thumb) | Loads a word from a label (Thumb). |
| ldr | LDR<c> <Rt>, [<Rn>, #+/-<imm>]{!} | Load/Store | A32 (Base) | Loads a word from memory. |
| ldr.w | LDR.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Word. |
| ldraa | LDRAA <Xt>, [<Xn|SP>, #<simm>] | Load/Store | PAC (Security) | Loads a value, authenticating the address with Key A. |
| ldrab | LDRAB <Xt>, [<Xn|SP>, #<simm>] | Load/Store | PAC (Security) | Loads a value, authenticating the address with Key B. |
| ldrb | LDRB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a byte from memory (zero-extended) using immediate offset. |
| ldrb | LDRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Loads a byte from memory (zero-extended) using register offset. |
| ldrb | LDRB<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a byte from memory (Zero extended). |
| ldrb.w | LDRB.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Byte. |
| ldrbt | LDRBT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a byte using User Mode permissions. |
| ldrd | LDRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] | Thumb Load | A32 (Base) | Loads two words from memory (Thumb). |
| ldrd | LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads two consecutive words into consecutive registers. |
| ldrex | LDREX <Rt>, [<Rn>] | Thumb Load Excl | A32 (Atomic) | Loads word and sets exclusive monitor (Thumb). |
| ldrex | LDREX<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Loads a word and marks physical address as exclusive. |
| ldrexb | LDREXB<c> <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Loads a byte and marks address as exclusive. |
| ldrexb | LDREXB <Rt>, [<Rn>] | Thumb Load Excl | A32 (Atomic) | Loads byte exclusively (Thumb). |
| ldrexd | LDREXD<c> <Rt>, <Rt2>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Loads a doubleword and marks address as exclusive. |
| ldrexh | LDREXH<c> <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Loads a halfword and marks address as exclusive. |
| ldrexh | LDREXH <Rt>, [<Rn>] | Thumb Load Excl | A32 (Atomic) | Loads halfword exclusively (Thumb). |
| ldrh | LDRH <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a halfword from memory (zero-extended). |
| ldrh | LDRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Loads a halfword from memory (zero-extended) using register offset. |
| ldrh | LDRH<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a halfword (Zero extended). |
| ldrh.w | LDRH.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Halfword. |
| ldrht | LDRHT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a halfword using User Mode permissions. |
| ldrsb | LDRSB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a byte and sign-extends it to 32-bits. |
| ldrsb | LDRSB <Xt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a byte and sign-extends it to 64-bits. |
| ldrsb | LDRSB<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a byte and sign-extends it. |
| ldrsb.w | LDRSB.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Signed Byte. |
| ldrsbt | LDRSBT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a signed byte using User Mode permissions. |
| ldrsh | LDRSH<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a halfword and sign-extends it. |
| ldrsh.w | LDRSH.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Signed Halfword. |
| ldrsht | LDRSHT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a signed halfword using User Mode permissions. |
| ldrsw | LDRSW <Xt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a word and sign-extends it to 64-bits. |
| ldrsw | LDRSW <Xt>, <label> | Load Literal | Base | Loads a word from PC-relative address and sign-extends to 64-bits. |
| ldrt | LDRT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a word using User Mode permissions (even if Privileged). |
| ldset | LDSET <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic bit set (OR) to memory. |
| ldsmax | LDSMAX <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic signed max to memory. |
| ldsmin | LDSMIN <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic signed min to memory. |
| ldtr | LDTR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Loads a word as if in EL0 (User mode). |
| ldumax | LDUMAX <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic unsigned max to memory. |
| ldumin | LDUMIN <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic unsigned min to memory. |
| ldur | LDUR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Loads a word using an unscaled immediate offset. |
| ldxp | LDXP <Wt1>, <Wt2>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads two words as an exclusive operation. |
| ldxr | LDXR <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a word and marks physical address as exclusive access. |
| lsl | LSLV <Wd>, <Wn>, <Wm> | Data Processing | Base | Shifts register left by variable amount. |
| lsl | LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Shift | SVE | Shifts elements left under predicate. |
| lsl | LSL{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Shifts a register left. |
| lsr | LSRV <Wd>, <Wn>, <Wm> | Data Processing | Base | Shifts register right by variable amount. |
| lsr | LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Shift | SVE | Shifts elements right logically under predicate. |
| lsr | LSR{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Shifts a register right. |
| madd | MADD <Wd>, <Wn>, <Wm>, <Wa> | Data Processing | Base | Calculates (Ra + (Rn * Rm)). |
| madd | MADD <Xd>, <Xn>, <Xm>, <Xa> | Data Processing | Base | Calculates (Xa + (Xn * Xm)). |
| mcr | MCR<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Writes a general-purpose register to a coprocessor register (e.g., CP15). |
| mcr2 | MCR2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Writes a general-purpose register to a coprocessor (Extension encoding). |
| mcrr | MCRR<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Writes two general-purpose registers to a coprocessor (64-bit transfer). |
| mcrr2 | MCRR2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Writes two registers to a coprocessor (Extension encoding). |
| mia | MIA<c> <Acc>, <Rn>, <Rm> | Coprocessor | A32 (XScale) | Multiplies two 32-bit values and adds to 40-bit internal acc (XScale Legacy). |
| miaph | MIAPH<c> <Acc>, <Rn>, <Rm> | Coprocessor | A32 (XScale) | SIMD multiply of packed halfwords to internal acc (XScale Legacy). |
| mla | MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies elements and adds to destination (Vd = Vd + Vn * Vm). |
| mla | MLA <Rd>, <Rm>, <Ra>, <Rn> | Thumb Mul | A32 (Base) | Rd = Rn + (Rm * Ra). |
| mla | MLA{S}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (Base) | Calculates Rd = (Rn * Rm) + Ra. |
| mls | MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies elements and subtracts from destination (Vd = Vd - Vn * Vm). |
| mls | MLS <Rd>, <Rm>, <Ra>, <Rn> | Thumb Mul | A32 (Base) | Rd = Rn - (Rm * Ra). |
| mls | MLS<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (Base) | Calculates Rd = Ra - (Rn * Rm). |
| mov | MOV <Vd>.<T>, <Vn>.<T> | SIMD Alias | NEON (SIMD) | Copies a vector register (Alias for ORR Vd, Vn, Vn). |
| mov | MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] | SIMD Copy | NEON (SIMD) | Moves a vector element to another vector element (Alias for INS). |
| mov | MOV{S}<c> <Rd>, <Operand2> | Data Proc | A32 (Base) | Moves a value into a register. |
| mov.w | MOV.W <Rd>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Move. |
| movi | MOVI <Vd>.<T>, #<imm8> {, lsl #<shift>} | SIMD Modified Imm | NEON (SIMD) | Moves an immediate value into every element of a vector. |
| movk | MOVK <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Base | Inserts a 16-bit immediate into a register, keeping other bits unchanged. |
| movn | MOVN <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Base | Moves inverted 16-bit immediate to register. |
| movt | MOVT<c> <Rd>, #<imm16> | Data Proc | A32 (Base) | Writes a 16-bit immediate to the top half of a register. |
| movw | MOVW<c> <Rd>, #<imm16> | Data Proc | A32 (Base) | Writes a 16-bit immediate to the bottom half, zeroing top. |
| movz | MOVZ <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Base | Moves 16-bit immediate to register, zeroing other bits. |