ARM Instructions
1145 instructions - showing 100 per page, page 7 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| rev16 | REV16 <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Reverse bytes in halfwords (Thumb). |
| rev16 | REV16 <Wd>, <Wn> | Data Processing | Base | Reverses bytes in each 16-bit halfword. |
| rev16 | REV16 <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bytes in each 16-bit halfword. |
| rev32 | REV32 <Xd>, <Xn> | Data Processing | Base | Reverses bytes in each 32-bit word (64-bit op). |
| revb | REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE Permute | SVE | Reverses bytes within 16/32/64-bit elements. |
| revh | REVH <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE Permute | SVE | Reverses halfwords within 32/64-bit elements. |
| revsh | REVSH <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Reverse bytes in low halfword, sign extend (Thumb). |
| revsh | REVSH <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bytes in low halfword and sign-extends. |
| revw | REVW <Zd>.D, <Pg>/M, <Zn>.D | SVE Permute | SVE | Reverses words within 64-bit elements. |
| rfe | RFE<c> <Rn>{!} | System | A32 (System) | Loads PC and CPSR from the stack. |
| rmif | RMIF <Xn>, #<shift>, #<mask> | Data Processing | FEAT_FlagM | Rotates a register and inserts bits into the Process State flags. |
| rndr | RNDR <Xt> | System | FEAT_RNG | Reads a random number from hardware entropy source. |
| rndrrs | RNDRRS <Xt> | System | FEAT_RNG | Reads a random number and requests reseed. |
| ror | ROR{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Rotates register right. |
| rorv | RORV <Wd>, <Wn>, <Wm> | Data Processing | Base | Rotates register right by variable amount. |
| rrx | RRX{S}<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Shifts register right by 1, inserting Carry flag into MSB. |
| rrx | RRX{S}.W <Rd>, <Rm> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Rotate Right with Extend. |
| rsb | RSB <Rd>, <Rn>, #0 | Thumb Data Proc | T32 (Thumb) | Reverse Subtract (Thumb 16-bit). |
| rsb | RSB{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Calculates Rd = Operand2 - Rn. |
| rsb.w | RSB.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit reverse subtract. |
| rsc | RSC{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Calculates Rd = Operand2 - Rn - NOT(Carry). |
| sadd16 | SADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of two signed 16-bit halfwords. |
| sadd8 | SADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of four signed 8-bit bytes. |
| saddl | SADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds lower/upper halves of signed vectors, producing wider result (Widening). |
| saddv | SADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Sums all active signed elements into a scalar result. |
| saddw | SADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds a wide vector to the lower/upper half of a narrow vector. |
| sb | SB | System Hint | A32 (v8.0) | Prevents speculative execution across the barrier (v8.0). |
| sb | SB | System Hint | Base (v8.0+) | Prevents speculative execution across the barrier. |
| sbc | SBC <Wd>, <Wn>, <Wm> | Data Processing | Base | Subtracts with borrow (Carry - 1). |
| sbc | SBC{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Calculates Rd = Rn - Operand2 - NOT(Carry). |
| sbc.w | SBC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit subtract with carry. |
| sbcs | SBCS <Wd>, <Wn>, <Wm> | Data Processing | Base | Subtracts with borrow and updates flags. |
| sbfm | SBFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Base | Extracts/Inserts bitfield with sign extension. |
| sbfx | SBFX<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | A32 (Base) | Extracts bits from a register and sign-extends them. |
| sbfx | SBFX <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Extracts and sign-extends bits. |
| scvtf | SCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts signed integers to floats. |
| scvtf | SCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>} | FP Conversion | Floating Point | Converts signed integer (GPR) to floating-point. |
| scvtf | SCVTF <Dd>, <Xn> | Float Conversion | F.P. | Converts signed integer (scalar) to floating-point. |
| sdiv | SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Divides signed integers. |
| sdiv | SDIV <Wd>, <Wn>, <Wm> | Data Processing | Base | Divides two signed registers. |
| sdiv | SDIV <Rd>, <Rn>, <Rm> | Thumb Div | A32 (Base) | Signed integer division. |
| sdiv | SDIV<c> <Rd>, <Rn>, <Rm> | Data Proc | A32 (Base) | Signed integer division. |
| sdot | SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | SVE Dot Product | SVE | Computes dot product of signed integers (AI Acceleration). |
| sdot | SDOT<c>.S8 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (DotProd) | Signed Dot Product (vector by vector). |
| sdot | SDOT <Vd>.4S, <Vn>.16B, <Vm>.16B | NEON DotProd | FEAT_DotProd | Dot product of signed integers (AArch64 NEON). |
| sdot | SDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B | SME2 DotProd | SME2 | Multi-vector signed dot product (SME2). |
| sel | SEL <Zd>.<T>, <Pg>, <Zn>.<T>, <Zm>.<T> | SVE Select | SVE | Selects elements from Zn or Zm based on predicate. |
| sel | SEL<c> <Rd>, <Rn>, <Rm> | Data Proc | A32 (DSP) | Selects bytes from Rn or Rm based on GE flags. |
| setend | SETEND <endian> | System | A32 (System) | Sets the endianness for data accesses (BE/LE). |
| setend | SETEND <endian> | Thumb System | T32 (System) | Set endianness (Thumb). |
| setf16 | SETF16 <Wn> | System | FEAT_FlagM | Sets PSTATE flags based on 16-bit operand. |
| setf8 | SETF8 <Wn> | System | FEAT_FlagM | Sets PSTATE flags based on 8-bit operand. |
| setpan | SETPAN #<imm> | System | A32 (System) | Enables/Disables PAN (Prevents kernel accessing user memory). |
| sev | SEV | System Alias | Base | Sends an event to all processors in the cluster (wakes up WFE). |
| sev | SEV | System Hint | A32 (Base) | Sends an event to all processors. |
| sev | SEV | Thumb System | T32 (Base) | Send event (Thumb). |
| sevl | SEVL | System Alias | Base | Sends an event locally to the executing processor. |
| sevl | SEVL | System Hint | A32 (Base) | Sends an event locally. |
| sevl | SEVL | Thumb System | T32 (Base) | Send local event (Thumb). |
| sha1c | SHA1C.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA1 hash update (Choose). |
| sha1c | SHA1C <Qd>, <Sn>, <Vm>.4S | Crypto | Crypto | SHA1 hash choose (AArch64 NEON). |
| sha1c | SHA1C <Qd>, <Sn>, <Vm>.<T> | Crypto | Crypto | SHA1 hash update (Choose function). |
| sha1h | SHA1H.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto | Updates SHA1 hash state. |
| sha1h | SHA1H <Sd>, <Sn> | Crypto | Crypto | SHA1 hash update (AArch64 NEON). |
| sha1m | SHA1M.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA1 hash update (Majority). |
| sha1m | SHA1M <Qd>, <Sn>, <Vm>.<T> | Crypto | Crypto | SHA1 hash update (Majority function). |
| sha1p | SHA1P.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA1 hash update (Parity). |
| sha1p | SHA1P <Qd>, <Sn>, <Vm>.<T> | Crypto | Crypto | SHA1 hash update (Parity function). |
| sha256h | SHA256H.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA256 hash update (part 1). |
| sha256h | SHA256H <Qd>, <Qn>, <Vm>.4S | Crypto | Crypto | SHA256 hash part 1 (AArch64 NEON). |
| sha256h | SHA256H <Qd>, <Qn>, <Vm>.<T> | Crypto | Crypto | SHA256 hash update (part 1). |
| sha256h2 | SHA256H2.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA256 hash update (part 2). |
| sha256h2 | SHA256H2 <Qd>, <Qn>, <Vm>.4S | Crypto | Crypto | SHA256 hash part 2 (AArch64 NEON). |
| sha256h2 | SHA256H2 <Qd>, <Qn>, <Vm>.<T> | Crypto | Crypto | SHA256 hash update (part 2). |
| sha256su0 | SHA256SU0.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto | SHA256 schedule update instruction 0. |
| sha256su1 | SHA256SU1.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA256 schedule update instruction 1. |
| sha512h | SHA512H.64 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SHA512) | SHA512 hash update part 1. |
| sha512h2 | SHA512H2.64 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SHA512) | SHA512 hash update part 2. |
| sha512su0 | SHA512SU0.64 <Qd>, <Qm> | Crypto 2-Reg | Crypto (SHA512) | SHA512 schedule update instruction 0. |
| sha512su1 | SHA512SU1.64 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SHA512) | SHA512 schedule update instruction 1. |
| shadd16 | SHADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed add and halving (average) of 2 halfwords. |
| shadd8 | SHADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed add and halving (average) of 4 bytes. |
| shl | SHL <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts elements left by immediate value. |
| shll | SHLL <Vd>.<Td>, <Vn>.<Ts>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts narrow vector left, extending to wide result. |
| shrn | SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts wide vector right, narrowing to destination (Upper/Lower). |
| shsub16 | SHSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed subtract and halving of 2 halfwords. |
| shsub8 | SHSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed subtract and halving of 4 bytes. |
| sli | SLI <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts source left and inserts into destination. |
| sm3partw1 | SM3PARTW1.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SM3) | SM3 schedule update part 1. |
| sm3partw2 | SM3PARTW2.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SM3) | SM3 schedule update part 2. |
| sm3ss1 | SM3SS1.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SM3) | SM3 cryptographic hash step 1. |
| sm3tt1a | SM3TT1A.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 2A. |
| sm3tt1b | SM3TT1B.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 2B. |
| sm3tt2a | SM3TT2A.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 3A. |
| sm3tt2b | SM3TT2B.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 3B. |
| sm4e | SM4E.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto (SM4) | SM4 encryption step. |
| sm4ekey | SM4EKEY.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto (SM4) | SM4 key schedule step. |
| smaddl | SMADDL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Multiplies two 32-bit registers, adds to 64-bit register (64-bit result). |
| smax | SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines maximum signed value per element. |
| smax | SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns larger signed integer per element. |