ARM Instructions
1145 instructions - showing 100 per page, page 9 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| strexd | STREXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Stores a doubleword if address is still exclusive. |
| strexh | STREXH<c> <Rd>, <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Stores a halfword if address is still exclusive. |
| strexh | STREXH <Rd>, <Rt>, [<Rn>] | Thumb Store Excl | A32 (Atomic) | Stores halfword exclusively (Thumb). |
| strh | STRH <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Stores the low halfword of a register. |
| strh | STRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Stores the low halfword of a register using register offset. |
| strh.w | STRH.W <Rt>, [<Rn>, #<imm>] | Thumb Store | T32 (Thumb2) | Thumb-2 32-bit Store Halfword. |
| strht | STRHT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Stores a halfword using User Mode permissions. |
| strt | STRT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Stores a word using User Mode permissions. |
| sttr | STTR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a register as if in EL0 (User mode). |
| sttrb | STTRB <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a byte as if in EL0. |
| sttrh | STTRH <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a halfword as if in EL0. |
| stur | STUR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a register using an unscaled immediate offset. |
| sturb | STURB <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a byte using an unscaled immediate offset. |
| sturh | STURH <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a halfword using an unscaled immediate offset. |
| stxp | STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores two registers if exclusive monitor matches. |
| stxr | STXR <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a word if exclusive monitor matches. |
| stxrb | STXRB <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a byte if exclusive monitor matches. |
| stxrh | STXRH <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a halfword if exclusive monitor matches. |
| stz2g | STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores Tag and zeros memory for two granules. |
| stzg | STZG <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag and zeros the data granule. |
| sub | SUB <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing | Base | Subtracts extended register from register. |
| sub | SUB <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing | Base | Subtracts immediate from register. |
| sub | SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing | Base | Subtracts shifted register from register. |
| sub | SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts elements of Vm from Vn. |
| sub | SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Subtracts vector Zm from Zdn under predicate. |
| sub | SUB{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Subtracts two values. |
| sub.w | SUB.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit subtract. |
| subg | SUBG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> | Data Processing | MTE (Memory Tagging) | Subtracts an immediate from an address, modifying the Allocation Tag (MTE). |
| subp | SUBP <Xd>, <Xn|SP>, <Xm|SP> | Data Processing | MTE (Memory Tagging) | Subtracts pointers ignoring Tags. |
| subps | SUBPS <Xd>, <Xn|SP>, <Xm|SP> | Data Processing | MTE (Memory Tagging) | Subtracts pointers (ignoring tags) and sets condition flags. |
| subs | SUBS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing | Base | Subtracts extended register and updates flags. |
| subs | SUBS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing | Base | Subtracts immediate and updates flags. |
| subs | SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing | Base | Subtracts shifted register and updates flags. |
| subs | SUBS PC, LR, #<imm> | Data Proc | A32 (Base) | Subs PC, LR, #imm (Exception return mechanism). |
| sudot | SUDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>[<index>] | NEON 3-Reg | FEAT_I8MM (AI) | Dot product of Signed Int8 and Unsigned Int8 (Indexed). |
| sunpkhi | SUNPKHI <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and sign-extends upper half of vector elements. |
| sunpklo | SUNPKLO <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and sign-extends lower half of vector elements. |
| svc | SVC #<imm> | Exception | System | Causes a Supervisor Call exception (to EL1). |
| svc | SVC #<imm> | Thumb System | T32 (Thumb) | System Call (Thumb encoding). |
| svc | SVC<c> #<imm> | System | A32 (System) | System call (formerly SWI). |
| swp | SWP <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic swap of a word. |
| swp | SWP<c> <Rt>, <Rt2>, [<Rn>] | Load/Store | A32 (Atomic) | Atomic swap word (Legacy). |
| sxtab | SXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends a byte from Rm and adds to Rn. |
| sxtab16 | SXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends two bytes and adds to two halfwords. |
| sxtah | SXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends a halfword and adds to Rn. |
| sxtb | SXTB <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Sign-extends byte to word (Thumb). |
| sxtb | SXTB<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Sign-extends the low byte (8-bits) to 32-bits. |
| sxtb | SXTB <Wd>, <Wn> | Bitfield | Base | Extracts the lowest 8 bits and sign-extends to 32 bits (Alias for SBFM). |
| sxtb16 | SXTB16<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends two bytes to two halfwords. |
| sxth | SXTH <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Sign-extends halfword to word (Thumb). |
| sxth | SXTH<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Sign-extends the low halfword (16-bits) to 32-bits. |
| sxtw | SXTW <Xd>, <Wn> | Bitfield | Base | Sign-extends a 32-bit register to 64 bits (Alias for SBFM). |
| sys | SYS #<op1>, Cn, Cm, #<op2> {, <Xt>} | System | System | Executes a system instruction (cache/TLB maintenance). |
| tbb | TBB [<Rn>, <Rm>] | Thumb Branch | T32 (Thumb) | PC-relative branch using a table of bytes (Switch statements). |
| tbh | TBH [<Rn>, <Rm>, LSL #1] | Thumb Branch | T32 (Thumb) | PC-relative branch using a table of halfwords. |
| tbl | TBL <Vd>.<T>, { <Vn>.16B, ... }, <Vm>.<T> | SIMD Table | NEON (SIMD) | Look up elements in a table of vectors using indices. |
| tbl | TBL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Looks up elements in a vector table using indices. |
| tbnz | TBNZ <Wt|Xt>, #<imm>, <label> | Branch | Base | Branches if specified bit is 1. |
| tbz | TBZ <Wt|Xt>, #<imm>, <label> | Branch | Base | Branches if specified bit is 0. |
| tcommit | TCOMMIT | System | TME (Transactional) | Commits the current transaction. |
| teq | TEQ<c> <Rn>, <Operand2> | Data Proc | A32 (Base) | Bitwise Exclusive OR and update flags (discard result). |
| teq.w | TEQ.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Test Equivalence (XOR and update flags). |
| tlbi | TLBI VMALLE1IS | System | Base (System) | Invalidates all TLB entries in the inner shareable domain. |
| tlbi | TLBI VAE1, <Xt> | System | Base (System) | Invalidates TLB entries by Virtual Address. |
| tlbi | TLBI <op> {, <Xt>} | System Alias | System | Invalidates Translation Lookaside Buffer entries. |
| trcit | TRCIT <Xt> | System | Trace | Generates a trace packet. |
| trn1 | TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Transposes elements (Lower). |
| trn1 | TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves even elements from two vectors. |
| trn2 | TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Transposes elements (Upper). |
| trn2 | TRN2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves odd elements from two vectors. |
| tsb | TSB CSYNC | System Hint | A32 (Trace) | Ensures trace generation is complete (v8.2). |
| tsb | TSB CSYNC | System Hint | Trace | Ensures trace generation is complete. |
| tst | TST<c> <Rn>, <Operand2> | Data Proc | A32 (Base) | Bitwise AND and update flags (discard result). |
| tst.w | TST.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Test (AND and update flags). |
| tstart | TSTART <Xd> | System | TME (Transactional) | Starts a memory transaction. Returns 0 if successful. |
| ttest | TTEST <Xd> | System | TME (Transactional) | Tests the transaction nesting depth. |
| uadd16 | UADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of two unsigned 16-bit halfwords. |
| uadd8 | UADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of four unsigned 8-bit bytes. |
| uaddl | UADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds lower/upper halves of unsigned vectors, producing wider result. |
| uaddv | UADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Sums all active unsigned elements into a scalar result. |
| uaddw | UADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds a wide vector to the lower/upper half of a narrow vector (Unsigned). |
| ubfm | UBFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Base | Extracts/Inserts bitfield (Zero Extend). |
| ubfx | UBFX<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | A32 (Base) | Extracts bits from a register and zero-extends them. |
| ubfx | UBFX <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Extracts and zero-extends bits. |
| ucvtf | UCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts unsigned integers to floats. |
| ucvtf | UCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>} | FP Conversion | Floating Point | Converts unsigned integer (GPR) to floating-point. |
| udf | UDF #<imm> | System | A32 (Base) | Permanently undefined instruction (generates Undefined Instruction exception). |
| udf | UDF #<imm> | Thumb System | T32 (Thumb) | Permanently undefined instruction (Thumb). |
| udiv | UDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Divides unsigned integers. |
| udiv | UDIV <Wd>, <Wn>, <Wm> | Data Processing | Base | Divides two unsigned registers. |
| udiv | UDIV <Rd>, <Rn>, <Rm> | Thumb Div | A32 (Base) | Unsigned integer division. |
| udiv | UDIV<c> <Rd>, <Rn>, <Rm> | Data Proc | A32 (Base) | Unsigned integer division. |
| udot | UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | SVE Dot Product | SVE | Computes dot product of unsigned integers. |
| udot | UDOT<c>.U8 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (DotProd) | Unsigned Dot Product (vector by vector). |
| udot | UDOT <Vd>.4S, <Vn>.16B, <Vm>.16B | NEON DotProd | FEAT_DotProd | Dot product of unsigned integers (AArch64 NEON). |
| udot | UDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B | SME2 DotProd | SME2 | Multi-vector unsigned dot product (SME2). |
| uhadd16 | UHADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned average of 2 halfwords. |
| uhadd8 | UHADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned average of 4 bytes. |
| uhsub16 | UHSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned halving subtract of 2 halfwords. |
| uhsub8 | UHSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned halving subtract of 4 bytes. |